Exercises — Communication interfaces — UART, SPI, I2C (master - slave), CAN bus

Map each clue to a column of the wiring figure above. (a) UART — asynchronous, only 2 signal wires (TX, RX) plus a shared ground, no clock line needed. (b) SPI — fastest (10s of Mbps), full-duplex, and one slave means the "one SS per slave" cost is tiny. (c) I2C — 2 signal wires (SDA, SCL) plus ground, shared by many addressed devices; no per-device select line. (d) CAN — differential (noise-immune, barely cares about ground) + message IDs that double as priority.

Idle = HIGH. The wake event is the START bit: a falling edge (HIGH→LOW). This is the "starting gun" for the receiver's stopwatch. (Remember: "HIGH" means high relative to the shared ground both chips connect to.) In the wiring figure, this is the falling edge that first appears on the TX→RX line.

"Released" = HIGH, made high by the pull-up resistor (the two resistors drawn on the I2C column of the figure). A chip can only pull LOW or let go; letting go = the resistor wins = HIGH. This is Wired-AND logic: LOW always beats HIGH.

WHAT: count bits, multiply by bit time. WHY: start/stop bits are on the wire too, so they count toward total time.

• Bits per character (8N1) $=1+8+1=10$.
• $t_{bit}=1/19200\approx 52.083\mu s$.
• Per char $=10\times 52.083=520.83\mu s$.
• 5 chars $=5\times 520.83=2604.17\mu s\approx 2.604\mathbf{ms}$.

Now bits/char $=1+8+1(\text{parity})+1=11$.

• Per char $=11\times 52.083=572.92\mu s$.
• 5 chars $=2864.58\mu s\approx 2.865\mathbf{ms}$. Why longer? One extra overhead bit per character — the parity bit costs time even though it carries no message data.

WHAT: solve the rise-time bound for $R_p$. WHY: too big a resistor → slow charging → the "let go = HIGH" edge is too lazy to reach threshold in time. $R_p<\frac{t_{r,\max }}{0.85C_b}=\frac{300\times 10^{-9}}{0.85\times 200\times 10^{-12}}.$ $=\frac{300\times 10^{-9}}{1.7\times 10^{-10}}\approx 1765\mathbf{\Omega }$. So pick $R_p\lesssim 1.76\text{k}\Omega$. What the figure below shows: three RC charging curves for the same $C_b=200\text{pF}$ but three different pull-ups. The orange curve ($1.0\text{k}\Omega$) crosses the dashed HIGH threshold well before the dotted $300\text{ns}$ deadline; the violet curve ($1.76\text{k}\Omega$) just barely makes the deadline (that's our answer, the limit); the magenta curve ($3.3\text{k}\Omega$) is still climbing past the deadline — too slow, the bus would fail at 400 kHz. Watching where each curve meets the dotted line is the derivation.

WHY MOSI + MISO + SCLK are shared (count once): these three carry data out, data in, and the clock. Every slave listens to the same clock and the same data lines — only the selected slave actually responds — so all slaves can hang off one copy of each. Sharing them costs nothing, so we count $3$ total. WHY one SS per slave (count $N$): SPI has no addressing. The only way the master says "I mean YOU" is by pulling that slave's own Slave Select line low. If two slaves shared an SS line, both would drive MISO at once and collide. So each slave needs its own dedicated SS → $N$ select lines for $N$ slaves. Shared: MOSI + MISO + SCLK $=3$. Selects: $1$ per slave $\times 6=6$. Total $=3+6=9$ wires (plus a common ground, implied). General rule: $3+N$ wires for $N$ slaves.

WHAT: the worst sample is the last one, where error has piled up most. WHY: each bit adds $\epsilon t_{bit}$ of drift; after $9.5$ bits the drift is $9.5\epsilon t_{bit}$, and it must stay under half a bit ($0.5t_{bit}$). $9.5\epsilon t_{bit}<0.5t_{bit}\Rightarrow \epsilon <\frac{0.5}{9.5}\approx 0.0526=5.26\%.$ That is why "±5% clock tolerance" is the folklore number for UART.

Line up the bits and remember: dominant/LOW (0) always wins on a wired-AND bus, and a master that sends 1 but reads 0 has lost. To avoid confusion, here are both counting conventions side by side. "Position number" counts from 1 (human order, left to right); "index" counts from 0 (programmer order).

position:  1  2  3  4  5  6  7
index   :  0  1  2  3  4  5  6
A       :  1  0  1  1  ...
B       :  1  0  1  0  ...
bus     :  1  0  1  0   <- diverges here

Positions 1–3 (indices 0–2) match. At position 4 = index 3, A sends 1 (recessive), B sends 0 (dominant). The bus reads 0. A sees it sent 1 but read 0 → A loses and backs off. B wins and continues uncorrupted. Why lowest value wins: the earliest 0 (dominant) drags the shared line down; sending a 1 there is the losing move. Same non-destructive idea as CAN arbitration.

WHY the factor 2: a dominant bit from the far node must reach the near node and let the far node hear the result within the same bit time — round-trip-worth of margin. $t_{bit}=1/(1\times 10^6)=1\mu s.$ $L\le \frac{v{t}_{bit}}{2}=\frac{2\times 10^8\times 1\times 10^{-6}}{2}=100\mathbf{m}.$ This is why classic CAN at 1 Mbps is limited to roughly 40–100 m depending on margins.

Lower bound (current the chip must sink): $R_p>\frac{V_{cc}-V_{OL}}{I_{OL,\max }}=\frac{3.3-0.4}{3\times 10^{-3}}=\frac{2.9}{0.003}\approx 967\mathbf{\Omega }.$ Upper bound (rise time): $R_p<\frac{t_{r,\max }}{0.85C_b}=\frac{1\times 10^{-6}}{0.85\times 250\times 10^{-12}}\approx 4706\mathbf{\Omega }.$ Allowed range: $967\Omega \lesssim R_p\lesssim 4.71\text{k}\Omega$. Check the common pick: is $2.2\text{k}\Omega$ inside the window? $967<2200<4706$ ✓ — yes, $2.2\text{k}\Omega$ sits comfortably between both fences (about $2.3\times$ above the lower bound and $2.1\times$ below the upper), so it is a safe standard choice. Why both bounds: too small starves the pull-down margin; too big starves the pull-up speed. The design lives inside the window. What the figure below shows: a number line of $R_p$ values. The magenta vertical line marks the lower fence ($967\Omega$, "sink enough current"); the violet line marks the upper fence ($4706\Omega$, "rise fast enough"); the shaded orange band between them is the allowed window; the navy dot at $2.2\text{k}\Omega$ shows our chosen value landing safely inside it.

SPI: each byte = 8 clock cycles; clock period $=1/(8\times 10^6)=125\text{ns}$. Time $=1024\times 8\times 125\text{ns}=1024\times 1000\text{ns}=1,024,000\text{ns}=1.024\text{ms}$. UART: each byte = 10 bits; $t_{bit}=1/115200\approx 8.681\mu s$. Time $=1024\times 10\times 8.681\mu s=1024\times 86.806\mu s\approx 88,889\mu s=88.9\text{ms}$. Ratio $=88.9/1.024\approx 86.8\times$ faster on SPI. Why so lopsided: SPI has no start/stop/parity framing and a far higher clock — serial speed is set by clock rate, not wire count.

Setup. After the start edge, the receiver waits $1.5t_{bit}$ to hit the centre of bit 0, then $1t_{bit}$ per subsequent bit. The centre of the last (stop-region) sample sits at $T_{last}=(N+1.5)t_{bit}.$ Drift. With per-bit clock error fraction $\epsilon$, accumulated timing error at $T_{last}$ is $\epsilon (N+1.5)t_{bit}$. Margin condition. To still land inside the half-bit window: $\epsilon (N+1.5)t_{bit}<0.5t_{bit}\Rightarrow \boxed{{\epsilon }_{\max }=\frac{0.5}{N+1.5}}.$ Evaluate $N=8$: ${\epsilon }_{\max }=\frac{0.5}{8+1.5}=\frac{0.5}{9.5}\approx 0.05263=5.26\%(\text{matches Problem 3.1}✓).$ Evaluate $N=9$: ${\epsilon }_{\max }=\frac{0.5}{9+1.5}=\frac{0.5}{10.5}\approx 0.04762=4.76\%.$ Why fewer data bits tolerate more error: less drift accumulates over a shorter frame. Longer frames demand tighter clocks. This is exactly why UART frames are kept short.

Choice: I2C. Wire count $=2$ signal wires (SDA + SCL), plus a shared ground, regardless of how many chips you add. Why not SPI: SPI needs one SS per slave → $3+3=6$ signal wires, and no addressing. I2C reaches each chip by its 7-bit address, so all three share the same two wires. Enabling feature: open-drain outputs + pull-up resistors implementing Wired-AND logic — every device can safely share one wire because it can only pull LOW or release, never fight another driver. Contrast with push-pull, which would short if two chips disagreed. Caveat (mastery detail): three identical chips may share the same fixed address → collision. Real designs need address-select pins or an I2C mux. (If the chips can't be re-addressed, fall back to SPI's per-chip SS.)

Step 1 — minimum bit time for this length. Arbitration needs a full round trip to fit inside one bit: $t_{bit}\ge \frac{2L}{v}=\frac{2\times 250}{2\times 10^8}=\frac{500}{2\times 10^8}=2.5\times 10^{-6}\text{s}=2.5\mu s.$ Step 2 — convert to bit rate. Bit rate is just the reciprocal of bit time: $B_{\max }=\frac{1}{t_{bit,\min }}=\frac{1}{2.5\times 10^{-6}}=400,000\text{bps}=400\mathbf{kbps}.$ Why you can't go faster: if $t_{bit}$ dropped below $2L/v$, a losing node would not yet have heard the far node's dominant bit come back before its own bit ended. It couldn't detect that it lost arbitration in time, two transmitters would keep driving, and the frame would corrupt. Distance and speed trade off: at a fixed length you cannot raise the bit rate past this ceiling without shortening the bus.

UART idle level ::: HIGH Event that wakes a UART receiver ::: the START bit (falling edge) Wire count for N SPI slaves (no daisy-chain) ::: 3 + N (plus a shared ground) Hidden wire every single-ended bus needs ::: a common ground (0 V reference) I2C "released" line level and cause ::: HIGH, held by the pull-up resistor CAN dominant bit ::: the 0 state, actively driven, always wins CAN recessive bit ::: the 1 state, released/floating, only survives if all nodes release Which ID wins CAN arbitration ::: the numerically LOWEST ID (most dominant/0 bits) UART clock tolerance for 8N1 ::: about ±5.26% (0.5/9.5) Two bounds on the I2C pull-up ::: lower from sink current, upper from rise time