Communication interfaces — UART, SPI, I2C (master - slave), CAN bus: Exercises

5.5.5 · D4 · Coding › Embedded Systems & Real-Time Software › Communication interfaces — UART, SPI, I2C (master - slave),

Shuru karne se pehle, ek reminder un symbols ka jo hum neeche baar baar use karte hain:

L1 — Recognition

L1 problems se pehle, yeh raha wiring picture — saare chaar interfaces side by side — har bus ki "shape" khud ek recognition cue hai. Dhyan do: UART TX↔RX cross karta hai; SPI har slave ke liye ek SS fan out karta hai; I2C do wires pull-ups ke through share karta hai; CAN ek single differential pair hai terminators ke saath.

Figure — Communication interfaces — UART, SPI, I2C (master - slave), CAN bus

Problem 1.1 (L1)

Chaar situations. Har ek ke liye, best interface batao (UART / SPI / I2C / CAN) aur ek word mein reason. (a) Ek microcontroller ek GPS module se 2-wire cable par baat karta hai, koi clock line available nahi. (b) Ek fast 20 MHz ADC padhna hai, full-duplex, sirf ek chip. (c) Barah chhote temperature sensors sirf do shared wires par lagane hain. (d) Ek car engine bay: sparks har jagah, kai controllers, message priority chahiye.

Recall Solution 1.1

Har clue ko upar wali wiring figure ke ek column se map karo. (a) UART — asynchronous, sirf 2 signal wires (TX, RX) plus shared ground, koi clock line nahi chahiye. (b) SPI — fastest (10s of Mbps), full-duplex, aur ek slave matlab "one SS per slave" ka cost bahut chhota hai. (c) I2C — 2 signal wires (SDA, SCL) plus ground, kai addressed devices share karte hain; koi per-device select line nahi. (d) CAN — differential (noise-immune, ground ki zyada parwah nahi) + message IDs jo priority bhi double karte hain.

Problem 1.2 (L1)

Ek idle UART line par, voltage HIGH hota hai ya LOW? Woh kaunsa ek event hai jo receiver ko jagaata hai?

Recall Solution 1.2

Idle = HIGH. Wake event hai START bit: ek falling edge (HIGH→LOW). Yahi receiver ki stopwatch ke liye "starting gun" hai. (Yaad raho: "HIGH" matlab high us shared ground ke relative jise dono chips connect karti hain.) Wiring figure mein, yeh woh falling edge hai jo pehli baar TX→RX line par appear hoti hai.

Problem 1.3 (L1)

I2C mein, SDA aur SCL dono open-drain hain. "Released" state mein (koi chip pull nahi kar rahi), wire kis level par baith-ti hai, aur kya cheez use wahan rakhti hai?

Recall Solution 1.3

"Released" = HIGH, jo pull-up resistor se high hota hai (figure ke I2C column par jo do resistors draw hain). Ek chip sirf LOW pull kar sakti hai ya chhood sakti hai; chhodna = resistor jeeta = HIGH. Yahi Wired-AND logic hai: LOW hamesha HIGH ko beat karta hai.

L2 — Application

Problem 2.1 (L2)

Ek UART 19200 baud, 8N1 par chalta hai (1 start, 8 data, no parity, 1 stop). 5-character string "Hello" bhejne mein kitna time lagega, milliseconds mein?

Recall Solution 2.1

KYA KARNA HAI: bits count karo, bit time se multiply karo. KYU: start/stop bits bhi wire par hote hain, isliye total time mein count hote hain.

Bits per character (8N1) $= 1 + 8 + 1 = 10$ .
$t_{bi t} = 1/19200 \approx 52.083 μ s$ .
Per char $= 10 \times 52.083 = 520.83 μ s$ .
5 chars $= 5 \times 520.83 = 2604.17 μ s \approx 2.604 ms$ .

Problem 2.2 (L2)

Same as upar lekin 8E1 (8 data + 1 even parity + 1 stop). Ab "Hello" ke liye total time?

Recall Solution 2.2

Ab bits/char $= 1 + 8 + 1 (parity) + 1 = 11$ .

Per char $= 11 \times 52.083 = 572.92 μ s$ .
5 chars $= 2864.58 μ s \approx 2.865 ms$ . Kyun zyada time? Har character mein ek extra overhead bit — parity bit time leta hai chahe woh koi message data carry nahi karta.

Problem 2.3 (L2)

Ek I2C bus 400 kHz par hai jiska total capacitance $C_{b} = 200 pF$ hai. Spec rise time ko $t_{r, m a x} = 300 ns$ par cap karta hai. $t_{r} \approx 0.85 R_{p} C_{b}$ use karke, sabse bada allowed pull-up $R_{p}$ nikalo.

Recall Solution 2.3

KYA KARNA HAI: rise-time bound ko $R_{p}$ ke liye solve karo. KYU: bahut bada resistor → slow charging → "let go = HIGH" edge itni lazy hai ki threshold tak time par nahi pahunchwi. $R_{p} < \frac{t _{r, m a x}}{0.85 C _{b}} = \frac{300 \times 1 0 ^{- 9}}{0.85 \times 200 \times 1 0 ^{- 12}} .$ $= \frac{300 \times 1 0 ^{- 9}}{1.7 \times 1 0 ^{- 10}} \approx 1765 Ω$ . Toh $R_{p} ≲ 1.76 k Ω$ chunna chahiye. Neeche wala figure kya dikhata hai: teen RC charging curves same $C_{b} = 200 pF$ ke liye lekin teen alag pull-ups ke saath. Orange curve ( $1.0 k Ω$ ) dashed HIGH threshold ko dotted $300 ns$ deadline se kafi pehle cross karta hai; violet curve ( $1.76 k Ω$ ) mushkil se deadline meet karta hai (yahi humara answer hai, limit); magenta curve ( $3.3 k Ω$ ) deadline ke baad bhi chadh raha hai — bahut slow, bus 400 kHz par fail ho jaata. Dekhna ki har curve dotted line se kahan milti hai yahi derivation hai.

Problem 2.4 (L2)

Ek SPI slave ko ek SS line har slave ke liye chahiye. Agar ek master ko 6 SPI slaves se baat karni ho (no daisy-chain), toh master se kul kitne wires niklenge? (MOSI, MISO, SCLK shared count karo, plus har slave ke liye ek SS.)

Recall Solution 2.4

KYU MOSI + MISO + SCLK shared hain (ek baar count karo): yeh teen data out, data in, aur clock carry karte hain. Har slave same clock aur same data lines sunता hai — sirf selected slave actually respond karta hai — toh sabhi slaves ek hi copy par hang off kar sakte hain. Inhe share karna kuch cost nahi karta, toh hum total $3$ count karte hain. KYU har slave ke liye ek SS (count $N$ ): SPI mein koi addressing nahi hai. Master ka yeh kehna ki "I mean YOU" sirf us slave ki apni Slave Select line low pull karke hota hai. Agar do slaves ek SS line share karein, dono MISO drive karenge aur collision hogi. Toh har slave ko apna dedicated SS chahiye → $N$ slaves ke liye $N$ select lines. Shared: MOSI + MISO + SCLK $= 3$ . Selects: $1$ per slave $\times 6 = 6$ . Total $= 3 + 6 = 9$ wires (plus ek common ground, implied). General rule: $N$ slaves ke liye $3 + N$ wires.

L3 — Analysis

Problem 3.1 (L3)

Ek UART receiver STOP bit ko 9.5 bit-times (8N1) ke baad sample karta hai. Ek taraf ka clock constant fraction $ε$ per bit se fast hai. Maximum $ε$ (percentage mein) kya hai, jisse pehle last sample half-bit margin se drift na kare?

Recall Solution 3.1

KYA: sabse bura sample last wala hota hai, jahan error sabse zyada pile up hoti hai. KYU: har bit $ε t_{bi t}$ drift add karta hai; $9.5$ bits ke baad drift $9.5 ε t_{bi t}$ hai, aur yeh half a bit ( $0.5 t_{bi t}$ ) se kam rehna chahiye. $9.5 ε t_{bi t} < 0.5 t_{bi t} \Rightarrow ε < \frac{0.5}{9.5} \approx 0.0526 = 5.26% .$ Isliye "±5% clock tolerance" UART ke liye folklore number hai.

Problem 3.2 (L3)

Do I2C masters lagbhag ek hi instant par start karte hain. Master A address bits 1 0 1 1 0 0 1 bhejta hai, Master B 1 0 1 0 1 1 0 (MSB first). Kis bit par collision resolve hoti hai, aur kaun jeetta hai? Wired-AND use karke explain karo.

Recall Solution 3.2

Bits ko line up karo aur yaad rakho: wired-AND bus par dominant/LOW (0) hamesha jeetta hai, aur jo master 1 bhejta hai lekin 0 padhta hai woh haar gaya. Confusion avoid karne ke liye, yahan dono counting conventions side by side hain. "Position number" 1 se count karta hai (human order, left to right); "index" 0 se count karta hai (programmer order).

position:  1  2  3  4  5  6  7
index   :  0  1  2  3  4  5  6
A       :  1  0  1  1  ...
B       :  1  0  1  0  ...
bus     :  1  0  1  0   <- yahan diverge hota hai

Positions 1–3 (indices 0–2) match karte hain. Position 4 = index 3 par, A 1 (recessive) bhejta hai, B 0 (dominant) bhejta hai. Bus 0 padhta hai. A dekhta hai usne 1 bheja lekin 0 padha → A haarta hai aur back off karta hai. B jeetta hai aur uncorrupted continue karta hai. Kyun lowest value jeetti hai: sabse pehla 0 (dominant) shared line ko neeche kheenchta hai; wahan 1 bhejna haarne wala move hai. Same non-destructive idea jaise CAN arbitration.

Problem 3.3 (L3)

Ek CAN bus ko 1 Mbps par chalna hai. Wire par signal speed $v = 2 \times 1 0^{8} m/s$ hai. $t_{bi t} \geq 2 L / v$ use karke, maximum bus length $L$ nikalo.

Recall Solution 3.3

KYU factor 2: far node ka ek dominant bit near node tak pahunchna chahiye aur far node ko bhi usi bit time mein result sunna chahiye — round-trip-worth of margin. $t_{bi t} = 1/ (1 \times 1 0^{6}) = 1 μ s .$ $L \leq \frac{v t _{bi t}}{2} = \frac{2 \times 1 0 ^{8} \times 1 \times 1 0 ^{- 6}}{2} = 100 m .$ Isliye classic CAN at 1 Mbps margins ke hisab se roughly 40–100 m tak limited hai.

L4 — Synthesis

Problem 4.1 (L4)

Design check: ek I2C bus, $V_{cc} = 3.3 V$ , itna current sink karna chahiye ki koi bhi device $V_{O L} = 0.4 V$ par $I_{O L, m a x} = 3 mA$ ke saath valid LOW hold kar sake. Iska $C_{b} = 250 pF$ bhi hai aur $t_{r, m a x} = 1 μ s$ (standard mode 100 kHz) meet karna hai. $R_{p}$ ki allowed range batao.

Recall Solution 4.1

Lower bound (current jo chip sink kare): $R_{p} > \frac{V _{cc} - V _{O L}}{I _{O L, m a x}} = \frac{3.3 - 0.4}{3 \times 1 0 ^{- 3}} = \frac{2.9}{0.003} \approx 967 Ω .$ Upper bound (rise time): $R_{p} < \frac{t _{r, m a x}}{0.85 C _{b}} = \frac{1 \times 1 0 ^{- 6}}{0.85 \times 250 \times 1 0 ^{- 12}} \approx 4706 Ω .$ Allowed range: $967 Ω ≲ R_{p} ≲ 4.71 k Ω$ . Common pick check: kya $2.2 k Ω$ window ke andar hai? $967 < 2200 < 4706$ ✓ — haan, $2.2 k Ω$ dono fences ke beech aaram se baitha hai (lower bound se ~ $2.3 \times$ upar aur upper bound se ~ $2.1 \times$ neeche), toh yeh ek safe standard choice hai. Kyun dono bounds: bahut chhota pull-down margin ko bhuka rakhta hai; bahut bada pull-up speed ko bhuka rakhta hai. Design window ke andar rehta hai. Neeche wala figure kya dikhata hai: $R_{p}$ values ki ek number line. Magenta vertical line lower fence ( $967 Ω$ , "enough current sink karo") mark karta hai; violet line upper fence ( $4706 Ω$ , "fast enough rise karo") mark karta hai; unke beech shaded orange band allowed window hai; navy dot $2.2 k Ω$ par humari chosen value safely andar dikhata hai.

Problem 4.2 (L4)

Tumhe ek flash chip se 1 KB (1024-byte) block move karna hai. Wall-clock transfer time compare karo: (a) SPI mode 0 at 8 MHz (8 clocks per byte, koi framing overhead nahi), vs (b) UART 8N1 at 115200 baud (10 bits per byte). Kaun fast hai aur kitne factor se (1 decimal tak round karo)?

Recall Solution 4.2

SPI: har byte = 8 clock cycles; clock period $= 1/ (8 \times 1 0^{6}) = 125 ns$ . Time $= 1024 \times 8 \times 125 ns = 1024 \times 1000 ns = 1, 024, 000 ns = 1.024 ms$ . UART: har byte = 10 bits; $t_{bi t} = 1/115200 \approx 8.681 μ s$ . Time $= 1024 \times 10 \times 8.681 μ s = 1024 \times 86.806 μ s \approx 88, 889 μ s = 88.9 ms$ . Ratio $= 88.9/1.024 \approx 86.8 \times$ faster on SPI. Kyun itna lopsided: SPI mein start/stop/parity framing bilkul nahi hai aur far higher clock hai — serial speed clock rate se set hoti hai, wire count se nahi.

L5 — Mastery

Problem 5.1 (L5)

$N$ -data-bit, 1 stop frame ke liye general UART clock-tolerance formula prove karo, jahan last-sampled bit centre start edge se $(N + 1.5)$ bit-times par hai. Dikhao $ε_{m a x} = \frac{0.5}{N + 1.5}$ , phir $N = 8$ aur $N = 9$ ke liye evaluate karo.

Recall Solution 5.1

Setup. Start edge ke baad, receiver $1.5 t_{bi t}$ wait karta hai bit 0 ke centre tak pahunchne ke liye, phir har subsequent bit ke liye $1 t_{bi t}$ . Last (stop-region) sample ka centre baithta hai $T_{l a s t} = (N + 1.5) t_{bi t} .$ Drift. Per-bit clock error fraction $ε$ ke saath, $T_{l a s t}$ par accumulated timing error hai $ε (N + 1.5) t_{bi t}$ . Margin condition. Half-bit window ke andar land karne ke liye: $ε (N + 1.5) t_{bi t} < 0.5 t_{bi t} \Rightarrow ε_{m a x} = \frac{0.5}{N + 1.5} .$ Evaluate $N = 8$ : $ε_{m a x} = \frac{0.5}{8 + 1.5} = \frac{0.5}{9.5} \approx 0.05263 = 5.26% (matches Problem 3.1 ✓) .$ Evaluate $N = 9$ : $ε_{m a x} = \frac{0.5}{9 + 1.5} = \frac{0.5}{10.5} \approx 0.04762 = 4.76% .$ Kyun kam data bits zyada error tolerate karte hain: chhote frame par kam drift accumulate hoti hai. Lamba frame tighter clocks demand karta hai. Isliye UART frames chhote rakhe jaate hain.

Problem 5.2 (L5)

Design + justify. Tumhe teen identical sensor chips ek microcontroller se connect karne hain. Har chip dono SPI aur I2C support karta hai. Cable run short hai, tumhe fewest wires chahiye aur teeno individually reachable hone chahiye. Interface choose karo, wire count batao, aur woh ek feature name karo jo us choice par >2 devices possible banata hai.

Recall Solution 5.2

Choice: I2C. Wire count $= 2$ signal wires (SDA + SCL), plus shared ground, chahe kitne bhi chips add karo. Kyun SPI nahi: SPI ko har slave ke liye ek SS chahiye → $3 + 3 = 6$ signal wires, aur koi addressing nahi. I2C har chip tak 7-bit address se pahunchta hai, toh teeno same do wires share karte hain. Enabling feature: open-drain outputs + pull-up resistors jo Wired-AND logic implement karte hain — har device safely ek wire share kar sakta hai kyunki woh sirf LOW pull ya release kar sakta hai, kabhi doosre driver se nahi lad sakta. push-pull se compare karo, jo short ho jaata agar do chips disagree karein. Caveat (mastery detail): teen identical chips same fixed address share kar sakte hain → collision. Real designs ko address-select pins ya I2C mux chahiye. (Agar chips re-address nahi ho sakti, toh SPI ke per-chip SS par fallback karo.)

Problem 5.3 (L5)

CAN sanity: ek network $L = 250 m$ span karna chahiye. $v = 2 \times 1 0^{8} m/s$ aur round-trip rule $t_{bi t} \geq 2 L / v$ ke saath, maximum bit rate (kbps mein) kya hai, aur kyun speed simply badh nahi sakti?

Recall Solution 5.3

Step 1 — is length ke liye minimum bit time. Arbitration ko ek full round trip ek bit ke andar fit karna chahiye: $t_{bi t} \geq \frac{2 L}{v} = \frac{2 \times 250}{2 \times 1 0 ^{8}} = \frac{500}{2 \times 1 0 ^{8}} = 2.5 \times 1 0^{- 6} s = 2.5 μ s .$ Step 2 — bit rate mein convert karo. Bit rate sirf bit time ka reciprocal hai: $B_{m a x} = \frac{1}{t _{bi t, m i n}} = \frac{1}{2.5 \times 1 0 ^{- 6}} = 400, 000 bps = 400 kbps .$ Kyun speed nahi badh sakti: agar $t_{bi t}$ $2 L / v$ se neeche gira, toh ek haarne wala node far node ka dominant bit wapas sunne se pehle apna bit khatam kar deta. Use pata nahi chalta ki woh haara, do transmitters drive karte rehte, aur frame corrupt ho jaata. Distance aur speed trade off karte hain: ek fixed length par tum bus chhota kiye bina bit rate is ceiling se upar nahi badh sakte.

Recall Self-test summary (cloze)

UART idle level ::: HIGH Woh event jo UART receiver ko jagata hai ::: START bit (falling edge) N SPI slaves ke liye wire count (no daisy-chain) ::: 3 + N (plus shared ground) Woh hidden wire jo har single-ended bus ko chahiye ::: common ground (0 V reference) I2C "released" line level aur cause ::: HIGH, pull-up resistor se hold hota hai CAN dominant bit ::: 0 state, actively driven, hamesha jeetta hai CAN recessive bit ::: 1 state, released/floating, sirf tabhi bachta hai jab sab nodes release karein CAN arbitration mein kaun jeetta hai ::: numerically LOWEST ID (sabse zyada dominant/0 bits) UART clock tolerance for 8N1 ::: about ±5.26% (0.5/9.5) I2C pull-up par do bounds ::: lower sink current se, upper rise time se