5.5.5 · D1Communication interfaces — UART, SPI, I2C (master - slave),
Ek wire sirf ek voltage carry kar sakti hai jo high ya low ho, time ke saath badlti rahe — aur kuch nahi. Har communication interface (UART, SPI, I2C, CAN) bas ek rulebook hai jo decide karta hai ki us up-and-down voltage ko bits mein kaise kata jaaye, kiski baari hai baat karne ki, aur kitni wires use karni hain.
Ye page — bilkul zero se — har wo symbol, term aur picture build karta hai jis par parent topic depend karta hai. Upar se neeche padho: har idea ek eent hai jis par agla idea khada hota hai.
Kisi bhi protocol se pehle, samjho ki ek wire hoti kya hai . Agar tum ek oscilloscope (ek "voltage camera") ko signal wire aur uske ground par lagao, toh tumhe ek graph dikhega: x-axis par time, y-axis par voltage upar ki taraf .
Definition Logic HIGH aur LOWDigital chips do voltage bands par agree karte hain. Ek threshold se upar voltage ka matlab hai logic 1 (HIGH) ; doosre threshold se neeche ka matlab hai logic 0 (LOW) . Ek chip jo kuch bhi "kehta" hai wo in do levels ki ek time mein sequence hai.
Upar wali picture poore subject ko ek frame mein dikh ata hai: wire do levels ke beech mein hilti hai, aur har protocol un hilne-dole ko meaning dene ka ek alag tarika hai. Ye graph apne dimaag mein rakho — baad ke har symbol isi par rehta hai.
Ek bit ek HIGH-ya-LOW decision hai — information ka sabse chhota tukda. Hamare voltage graph par ye ek time-slot hai jo ya toh upar hai ya neeche.
Ek byte 8 bits ka ek group hai, 0x41 jaisa likha jaata hai. 0x prefix ka matlab hai "aage wala base-16 (hexadecimal) mein padho." 0x41 = 4 × 16 + 1 = 65 'A'.
Intuition Hex kyun, decimal kyun nahi?Ek hex digit exactly 4 bits encode karta hai (0000–1111), toh do hex digits = ek byte, saaf-saaf. Decimal binary ke saath align nahi karta; hex karta hai. Bas yahi ek wajah hai ki ye is chapter mein har jagah hai.
LSB = Least Significant Bit = woh bit jo 2 0 = 1 MSB = Most Significant Bit, jo 2 7 = 128 time mein pehle bhejti hai. UART aisa karta hai; byte dobara banane ke liye tumhe order pata hona chahiye.
Common mistake Bits ko galat order mein padhnaKyun sahi lagta hai: hum numbers MSB-first likhte hain (left-to-right), toh hum assume karte hain ki wo usi tarah travel karte hain. Reality: UART LSB-first bhejta hai. Agar tum scope se left-to-right padho toh tumhe byte bit-reversed milega. Hamesha check karo ki kaunsa end pehle jaata hai.
Ab ki ek bit ek time-slot occupy karti hai, humein jaanna hai ki wo slot kitna wide hai.
B Baud B bits/second (bps) speed hai.
Greek letter ε Baud rate & clock generation (timers/PLL) ki chip ye rate apne crystal se actually kaise banati hai.
Is poore chapter ka sabse gehra fark hai: kya koi alag wire beat carry karti hai?
Ek clock ek wire hai jo steady beat par HIGH-LOW-HIGH-LOW tick karta hai. Iske edges (wo pal jab wo flip karta hai) receiver ko batate hain "abhi — data wire ko is pal padho."
Definition Synchronous vs Asynchronous
Synchronous = hota hai ek shared clock wire (SPI, I2C). Data exactly tab padha jaata hai jab clock tick kare — jaise dancers kisi conductor ko dekh rahe hon.Asynchronous = koi clock wire nahi (UART, CAN). Dono sides pehle se t bi t
Intuition Async ko "starting gun" kyun chahiyeShared beat ke bina, receiver ko jaanna chahiye kab counting shuru karni hai . Ek special pehla bit (UART ka START bit) pistol ka shot hai; phir receiver har expected slot ke middle mein sample karta hai (figure mein ↓ arrows dekho) taaki chhoti timing errors use galat slot mein na dhakele.
Synchronous protocols "kaunsa edge " ki baat karte hain. Bilkul yehi hai edge.
Definition Rising / falling edgeEk rising edge woh pal hai jab ek wire LOW→HIGH jaaye (↑). Ek falling edge HIGH→LOW (↓) hai. Chips edge par act karte hain, level par nahi, kyunki edge ek sharp, unambiguous moment hai. Yahi wajah hai ki SPI ke CPOL/CPHA settings (parent mein) saari kaunsa edge sample kare ke baare mein hain.
Definition Topology ke words
Point-to-point : bilkul do devices, unke beech ek wire pair (UART).Bus : kai devices saari ek hi shared wires par tap kiye hue (I2C, CAN).Master : wo device jo transfer shuru karta hai aur (SPI/I2C ke liye) clock generate karta hai.Slave : ek device jo sirf tab respond karta hai jab usse baat ki jaaye.Multi-master : kai devices mein se har ek ko transfer start karne ki permission hai, toh collisions ke liye ek rule chahiye.
Jab kai devices ek wire share karte hain, ek naya khatara aata hai: unme se do ek saath use drive karein. Ye seedha agle idea par le jaata hai.
Definition Push-pull outputEk push-pull output wire ko HIGH aur LOW dono actively drive kar sakta hai — ye use upar push karta hai ya neeche pull karta hai. Point-to-point ke liye badhiya (UART, SPI), shared bus par fatal: agar ek chip HIGH push kare jabki doosra LOW pull kare, toh short circuit ho jaata hai (left panel dekho — do arrows ladh rahe hain).
Definition Open-drain output + pull-upEk open-drain output sirf LOW pull ya chhod (float) kar sakta hai — ye kabhi HIGH push nahi kar sakta. Ek shared pull-up resistor wire ko gently HIGH se jodta hai jab bhi sab chhod dein. Toh released state = HIGH, aur koi bhi device LOW pull kare toh jeet jaaye bina larai ke (right panel). Yahi I2C ko safe banata hai. Poori detail Open-drain vs Push-pull outputs mein.
Definition Wired-AND logicKyunki LOW hamesha jeetta hai, wire ki value HIGH hoti hai sirf tabhi jab har device ne use chhoda ho — yaani saare outputs ka logical AND. Yahi wired-AND hai, wo physics trick jo I2C addressing aur CAN arbitration dono ke peeche hai. Dekho Wired-AND logic .
Mnemonic Kaun jeetta hai?Open-drain: LOW hamesha jeetta hai. LOW ek haath hai jo rope pakad raha hai; HIGH matlab sab ne chhod diya. Ek pakad hazaar chhodne ko haar deta hai.
Definition Single-ended signalEk single-ended wire ki value uski voltage hai jo ek shared ground ke against measure ki jaaye. Simple, lekin koi bhi electrical noise jo wire ko utha de reading bhi corrupt kar deta hai (UART, SPI, I2C single-ended hain).
Definition Differential signalEk differential pair (CAN ka CANH, CANL) bit ko fark V C A N H − V C A N L
Intuition Difference noise kyun cancel karta haiNoise dono wires ko lagbhag barabar affect karta hai (wo twisted hain saath mein). Dono wires mein same jolt + n fark unchanged chhod deta hai: ( V H + n ) − ( V L + n ) = V H − V L Differential signaling & noise immunity mein.
Definition Dominant vs recessiveCAN par ek 0 bit dominant hai (actively driven, jeetta hai) aur ek 1 bit recessive hai (weak, haarta hai) — phir wired-AND, toh kisi bhi node ka 0 ek 1 ko override karta hai. Yahi hai CAN ka kaun-pehle-bolta-hai resolve karna (bitwise arbitration).
Definition Quick symbol glossary
B t bi t = 1/ B ε fractional clock error (jaise 0.05 = 5% R p Ω C b t r V cc V O L t p r o p L v 2 × 1 0 8
I2C sharing and CAN arbitration
Single-ended vs Differential
Vault mein related building blocks: Serial vs Parallel communication , Shift registers , Interrupts vs Polling , Bit stuffing & CRC in CAN frames .
Daayeen taraf cover karo; reveal karne se pehle kya tum jawab de sakte ho?
Wire physically kya carry karta hai? Ek voltage jo HIGH ya LOW ho, time ke saath badlti rahe — aur kuch nahi.
Ek bit kya hota hai? Ek HIGH-ya-LOW decision; information ki sabse chhoti unit.
0x41 ko decimal aur ek letter mein convert karo.4 × 16 + 1 = 65 'A'.
LSB-first ka matlab kya hai? 2 0
Bit-time formula aur 9600 baud par t bi t t bi t = 1/ B = 1/9600 ≈ 104.2 μ s
Synchronous aur asynchronous mein fark? Synchronous mein shared clock wire hoti hai; asynchronous mein bit time pehle se agree hota hai aur self-timing hoti hai.
Rising edge aur falling edge kya hai? Rising = LOW→HIGH (↑); falling = HIGH→LOW (↓).
Do push-pull outputs ek bus wire kyun share nahi kar sakte? Ek HIGH push kare jabki doosra LOW pull kare toh short circuit hota hai.
Open-drain mein kaun sa level hamesha jeetta hai aur kyun? LOW — ek device sirf low pull ya float kar sakta hai, aur pull-up float=HIGH banata hai, toh koi bhi pull-low dominate karta hai (wired-AND).
Differential pair noise kyun reject karta hai? Noise dono wires mein barabar add hota hai; receiver difference padha karta hai, toh cancel ho jaata hai: ( V H + n ) − ( V L + n ) = V H − V L
CAN par kaun sa bit dominant hai, 0 ya 1? 0 dominant hai (jeetta hai); 1 recessive hai (haarta hai).
Pull-up rise ko e − t / R p C b Wire ek RC circuit hai jo V cc