Before you can read LOAD R1, [[100]] and know it means "two trips to memory," you need a handful of tiny building blocks. This page builds every one of them from nothing, in the order they stack. This is a self-contained foundations page: every symbol used anywhere in this topic is defined right here, so you never have to look elsewhere for what a piece of notation means.
Figure s01 below draws this street. Look at the purple box: the label "box 100" sitting on top is the address; the big number 200inside is the content. The whole topic is the game of telling these two apart, so fix this picture in your mind.
The two ideas you must keep separate forever:
Address = the label on the box (e.g. 100).
Content = what is stored inside box 100 (e.g. 200).
These are different numbers that live in the same world of numbers, which is exactly why beginners confuse them. The whole topic is a game of "is this number an address or a value?"
Related vault reading: Memory Hierarchy and Access Latency explains why reaching a mailbox is slow compared to holding a value in your hand.
Figure s02 puts the two worlds side by side: the butter-coloured CPU on the left holds a few pocket-registers (R1, R2, R3); the lavender memory street on the right holds many boxes. Notice the coral double-arrow labelled "slow bus trip" — that trip is what register and immediate modes avoid entirely.
Note the deliberate symmetry with memory: M[x] opens memory box x; R[i] opens register i. Same "open the container" idea, two different containers — one slow (street), one fast (pocket).
Figure s03 cuts one instruction into its coloured fields: the opcode (what to do), the mode tag (how to read the number), the destination register, and the operand number A. The take-away the arrows point at: the same bits 100 mean different things depending on the mode tag beside them.
Deeper mechanics live in Instruction Encoding & Opcodes and CPU Datapath and Control Unit (the hardware that actually reads and obeys the fields).
Figure s04 shows the array as a row of boxes from box 100 onward. Follow the mint arrow: it walks R[i]=4 boxes forward from the base, landing on the coral box — the effective address 104. The label stresses this walk is an addition, not a memory read, which is exactly why indexed costs only 1 access.
Read it bottom-up: boxes and pockets give you the two "open" symbols; the instruction gives you A; addition and pointers give you the ways to transform A; all of it converges on the effective address, and every mode is just one way to compute it — for a read or a write alike.
Below, each line is a self-test in Question ::: Answer form: read the question, say your answer out loud, then check it against the text after the triple colon.
An address is…
the label/number of a memory box (which box), not what's inside it.
The content at an address is…
the value stored inside that box; a different notion from the address itself.
M[x] means…
the content stored at memory address x — "open box x"; on the left of an arrow it means write into box x.
How many memory reads does M[M[100]] require?
two — one to read box 100, one to read the box whose number that gave.
R[i] means…
the content of register i, a fast slot inside the CPU; i ranges over the fixed set 0..N−1 (N often 8, 16, or 32).
Why do register and immediate modes cost 0 memory accesses?
their operand is inside the CPU (a register / the instruction word already fetched) — no memory street trip.
What does "no EA" mean for immediate/register mode?
the operand isn't in memory, so there is no box to open and no address to compute — EA simply does not apply.
In this topic the symbol A is…
the fixed number written in the instruction's operand field; the mode decides how it's used.
Register-indirect vs memory-indirect?
register-indirect EA=R[i] (1 access, pointer in a register); memory-indirect EA=M[A] (2 accesses, pointer in memory).
Why is EA=A+R[i] (indexed) faster than EA=M[A] (memory-indirect)?
indexed does an addition of values already held (no memory trip); memory-indirect does an extra memory read.
What is PC-relative addressing?
EA=PC+A — an offset A from the current instruction's address, used for branches and position-independent code.
Do stores use a different EA recipe than loads?
no — EA is computed identically; the store just writes M[EA]←value on the final trip instead of reading.