ALU — operations, flags (zero, carry, overflow, negative): Worked examples

The four flags in one breath (so no symbol is unearned)

Before the matrix, let us re-anchor the four flags in plain words + one picture so nothing below uses a symbol you haven't met.

Picture the 8 bits as 8 boxes in a row, numbered from the right: box 0, box 1, … up to box 7 on the far left. Box 7 is special — it is the top box (MSB).

Figure — ALU — operations, flags (zero, carry, overflow, negative)

The scenario matrix

Every ALU flag puzzle is one of these cells. The goal: hit all of them below.

#	Cell (the situation)	What's being tested	Example
A	Add, both small positives	clean case, all flags calm	Ex 1
B	Add, unsigned carry but signed is correct	C=1, V=0 (independent!)	Ex 2
C	Add, signed overflow but no carry	C=0, V=1 (independent!)	Ex 3
D	Add, negatives that overflow (neg+neg→pos)	C=1 and V=1 together	Ex 4
E	Subtract, $A < B$ (borrow / negative result)	subtract carry = borrow logic	Ex 5
F	Subtract, $A \geq B$ , result positive	subtract carry = "no borrow"	Ex 6
G	Subtract equal values → zero (degenerate)	Z=1 on subtract, $x - x = 0$	Ex 7
H	Logic op (AND / XOR) — flags behave differently	C and V forced to 0	Ex 8
I	Shift left — the "carry catches the falling bit"	C from shifted-out bit	Ex 9
J	Real-world + exam twist (sensor wraparound)	apply flags to a decision	Ex 10

Ten cells, ten examples. Every numeric answer at the bottom is machine-checked.

Example 1 — Cell A: the calm case

Worked example Add

$A = 18$ , $B = 3$ (8-bit) Forecast: before reading on, guess all four flags. (Both numbers are tiny and positive — do you expect any flag lit?)

Write both in binary. $18 = 00010010$ , $3 = 00000011$ . Why this step? Flags are computed from bits, not decimals, so we must see the boxes.
Add column by column: $00010010 + 00000011 = 00010101$ . Why this step? This is the actual adder output; $00010101 = 21$ .
Z: any box lit? Yes (boxes 0,2,4). So $Z = 0$ . Why this step? Z is NOR of all bits; a single 1 kills it.
N: box 7 is 0, so $N = 0$ . Why this step? N is literally the top box.
C: nothing fell off the left, $c_{8} = 0$ , so $C = 0$ . Why this step? $18 + 3 = 21 < 256$ , unsigned fits.
V: pos + pos gave pos, sign never flipped, $V = 0$ . Why this step? Carry into box 7 = 0, carry out = 0, $0 \oplus 0 = 0$ .

Verify: $18 + 3 = 21$ , and $0001010 1_{2} = 21$ . Both signed ( $21$ ) and unsigned ( $21$ ) readings agree — a calm result has all flags 0. ✓

Example 2 — Cell B: unsigned carry, signed is correct

Worked example Add

$A = 255$ , $B = 1$ (8-bit) Forecast: signed, $255$ is really $- 1$ . So this is $- 1 + 1$ . Guess: which flag lights, C or V?

Binary: $255 = 11111111$ , $1 = 00000001$ . Why this step? $11111111$ is all boxes lit — the classic "about to wrap" pattern.
Add: $11111111 + 00000001 = 100000000$ . Keep 8 boxes → $00000000$ . Why this step? The 9th "1" cannot be stored; it falls off the left edge.
C: a 1 fell off → $c_{8} = 1$ , so $C = 1$ . Why this step? Unsigned $255 + 1 = 256 > 255$ , out of unsigned range.
Z: every box is 0 → $Z = 1$ . Why this step? NOR over all-zero bits is 1.
N: box 7 is 0 → $N = 0$ .
V: carry into box 7 was $c_{7} = 1$ , carry out was $c_{8} = 1$ , and $1 \oplus 1 = 0$ , so $V = 0$ . Why this step? They agree, so no signed overflow. Signed view: $- 1 + 1 = 0$ — exactly right!

Verify: unsigned $256 mod 256 = 0$ ; signed $- 1 + 1 = 0$ . Result is $0$ , $C = 1$ , $V = 0$ : a big unsigned carry with a perfectly correct signed answer. C and V are independent. ✓

Example 3 — Cell C: signed overflow, no carry

Worked example Add

$A = 127$ , $B = 1$ (8-bit) Forecast: signed max is $+ 127$ . What is $127 + 1$ supposed to be, and can 8 signed bits hold it? Guess C and V.

Binary: $127 = 01111111$ , $1 = 00000001$ . Why this step? $01111111$ is the largest positive signed value — box 7 empty, all others full.
Add: $01111111 + 00000001 = 10000000$ . Why this step? The carry ripples up and lands inside box 7, flipping it to 1.
N: box 7 is now 1 → $N = 1$ . Why this step? The sign bit flipped from + to −.
C: did anything leave box 7? No, $c_{8} = 0$ , so $C = 0$ . Why this step? Unsigned $127 + 1 = 128 \leq 255$ , fits fine unsigned.
V: carry into box 7 was $c_{7} = 1$ (that's what flipped it), carry out $c_{8} = 0$ . $1 \oplus 0 = 1$ , so $V = 1$ . Why this step? Signed answer should be $128$ , but max signed is $127$ ; it wrapped to $- 128$ . Overflow!

Verify: result $10000000 = 128$ unsigned $= - 128$ signed. $127 + 1 = 128 \neq = - 128$ , so signed is wrong → $V = 1$ . Unsigned $128$ is correct → $C = 0$ . Mirror image of Example 2. ✓

Example 4 — Cell D: negatives that overflow (C=1 and V=1)

Worked example Add

$A = - 100$ , $B = - 50$ (8-bit signed) Forecast: true sum $- 150$ . Signed range bottom is $- 128$ . Can it hold $- 150$ ? Guess both flags.

Encode in two's complement. $- 100$ : $100 = 01100100$ , invert $= 10011011$ , $+ 1 = 10011100$ . $- 50$ : $50 = 00110010$ , invert $= 11001101$ , $+ 1 = 11001110$ . Why this step? The adder only understands bit patterns; we must convert both negatives via invert-and-add-1.
Add: $10011100 + 11001110 = 101101010$ . Keep 8 → $01101010$ . Why this step? Two "big" patterns add past 8 boxes, so a 1 falls off the left.
C: a 1 fell off → $c_{8} = 1$ , so $C = 1$ . Why this step? Unsigned view: $156 + 206 = 362 > 255$ .
N: box 7 of $01101010$ is 0 → $N = 0$ . Why this step? Two negatives produced a positive-looking result — the classic overflow tell.
V: carry into box 7? Adding box-7 bits $1 + 1$ plus incoming carry $0$ gives $10$ , so $c_{7} = 0$ into box 7... let us use the sign rule instead: neg + neg → the result's sign came out positive ( $N = 0$ ). Sign flipped wrongly → $V = 1$ . Why this step? "Same signs in, sign flips out = overflow." Both inputs negative, output positive → overflow.

Verify: $01101010 = 106$ signed. But $- 100 + - 50 = - 150$ , and $- 150$ wrapped: $- 150 + 256 = 106$ . Signed answer wrong ( $V = 1$ ), unsigned carry happened ( $C = 1$ ). Both flags lit at once. ✓

Example 5 — Cell E: subtract with a borrow ( $A < B$ )

First, let us build the subtract-carry rule so no symbol is unearned.

Worked example Compute

$A - B$ with $A = 3$ , $B = 5$ Forecast: $3 - 5 = - 2$ . Since $A < B$ , will $C$ be 1 or 0?

$\sim B$ : $B = 00000101$ , flip → $\sim B = 11111010$ . Why this step? Turns subtraction into an addition the ALU already knows.
Add with carry-in 1: $00000011 + 11111010 + 1 = 11111110$ . Why this step? The "+1" completes the two's-complement negation of $B$ .
R $= 11111110$ . As signed: invert $\to 00000001$ , $+ 1 \to 00000010 = 2$ , so value $= - 2$ . Why this step? Reading a two's-complement negative back to decimal.
C: carry out of box 7 here is $0$ → $C = 0$ → borrow occurred. Why this step? $3 < 5$ , so subtraction had to borrow; the ALU signals that via $C = 0$ .
N: box 7 is 1 → $N = 1$ (negative). Z: not zero → $Z = 0$ .
V: pos $-$ pos $=$ pos $+$ neg (opposite signs) → cannot overflow → $V = 0$ . Why this step? Opposite-sign additions never leave signed range.

Verify: $3 - 5 = - 2$ , matches. $C = 0$ correctly flags " $A < B$ " — this is exactly the test a `BCC` (branch if carry clear) uses for unsigned <. ✓

Example 6 — Cell F: subtract, $A \geq B$ , positive result

Worked example Compute

$A - B$ with $A = 200$ , $B = 80$ Forecast: $200 - 80 = 120 \geq 0$ , and $A \geq B$ . Guess $C$ .

$B = 80 = 01010000$ , $\sim B = 10101111$ . Why this step? Prepare the addition form.
$A = 200 = 11001000$ . Add: $11001000 + 10101111 + 1 = 101111000$ . Keep 8 → $01111000$ . Why this step? A 1 falls off the left → that becomes the carry.
R $= 01111000 = 120$ . Why this step? Box 7 empty → positive; $64 + 32 + 16 + 8 = 120$ .
C: carry out $= 1$ → no borrow → confirms $A \geq B$ (unsigned $200 \geq 80$ ). Why this step? On subtract, $C = 1$ is the "greater-or-equal" signal.
N $= 0$ (box 7 empty). Z $= 0$ . V: $200$ and $80$ are unsigned here; signed-wise $200 = - 56$ , so $- 56 - 80 = - 136$ would overflow... but we asked for the unsigned subtraction interpretation. As pure signed: $- 56 - 80 = - 136 < - 128 \Rightarrow V = 1$ . Interpretation matters — see below. Why this step? Same bits, two stories: unsigned answer $120$ is right ( $C = 1$ ), but if these were signed numbers, $V = 1$ warns the signed answer wrapped.

Verify: unsigned $200 - 80 = 120$ (result bits give 120, $C = 1$ ). Signed $- 56 - 80 = - 136$ , which is $< - 128$ so $V = 1$ . The ALU sets both $C$ and $V$ ; you pick which to read based on whether you meant signed or unsigned. ✓

Example 7 — Cell G: degenerate — subtract equal values → zero

Example 8 — Cell H: logic op forces C and V to 0

Example 9 — Cell I: shift left, carry catches the falling bit

Example 10 — Cell J: real-world + exam twist

Worked example A temperature sensor stores its reading in an

8-bit unsigned register (valid $0..255$ ). It reads $250$ , then rises by $10$ . The firmware does ADD reg, #10 and branches on the carry flag to trigger a "SENSOR SATURATED" warning. Does the warning fire, and what value does the register hold? Forecast: $250 + 10 = 260$ . Register max is $255$ . Guess the stored value and $C$ .

$250 = 11111010$ , $10 = 00001010$ . Why this step? Convert to bits to run the real adder.
Add: $11111010 + 00001010 = 100000100$ . Keep 8 → $00000100 = 4$ . Why this step? $260 > 255$ , so a 1 falls off the left → wraparound.
C $= 1$ → the BCS (branch if carry set) fires → warning triggers. Why this step? $C$ is the unsigned out-of-range signal, exactly what "sensor maxed out" means.
Register now holds $4$ , a nonsense low value — the wraparound hazard. Why this step? Without checking $C$ , firmware would think temperature dropped to 4. The flag is the only surviving record of the lost 9th bit.
Exam twist: if the same registers were signed, would you read $V$ instead? $250$ signed $= - 6$ , $10$ signed $= 10$ ; $- 6 + 10 = 4$ , which fits $[- 128, 127]$ → $V = 0$ . Opposite signs can't overflow. Why this step? Same bits, different flag matters: unsigned firmware watches $C$ , signed logic watches $V$ .

Verify: $(250 + 10) mod 256 = 4$ , and $260 \geq 256 \Rightarrow C = 1$ (warning). Signed reading $- 6 + 10 = 4$ , in range $\Rightarrow V = 0$ . The flags register holds both; the branch chosen decides which one steers the code. ✓

Matrix coverage check

Recall Did we hit every cell?

A→Ex1, B→Ex2, C→Ex3, D→Ex4, E→Ex5, F→Ex6, G→Ex7, H→Ex8, I→Ex9, J→Ex10. Signs covered: pos+pos, neg+neg, pos−pos both directions, mixed. Degenerate zero covered. Logic and shift (where C/V change meaning) covered. Real-world wraparound covered. ✓

Recall When two examples have identical bits but different flags, what decides?

The interpretation you chose (signed vs unsigned) ::: The bits and all four flags are computed the same way every time; you pick $C$ for unsigned decisions and $V$ for signed decisions. The ALU never assumes.

Given

A = 127

B = 1

, 8-bit ADD: which flag is set and which is clear?

V = 1

(signed overflow),

C = 0

(no unsigned carry).

On a subtract, what does

C = 0

tell you about

A

and

B

A borrow happened, i.e.

A < B

(unsigned).

For XOR, why are

C

and

V

forced to 0?

No bit crosses a box boundary in a logic op, so carry and signed-overflow are meaningless.

Connections

Parent · ALU operations & flags
Two's Complement Representation
Full Adder and Ripple-Carry Adder
Condition Codes and Conditional Branches
Status / Flags Register (PSR / EFLAGS)
Signed vs Unsigned Comparison Instructions
Combinational vs Sequential Logic