ALU — operations, flags (zero, carry, overflow, negative): Question bank

Quick vocabulary reminder so no symbol appears "for free":

$A$ , $B$ — the two $n$ -bit input numbers (operands).
$R$ — the $n$ -bit result the ALU produces.
$r_{n - 1}$ — the most significant bit (MSB): the leftmost, highest-value bit of $R$ .
$c_{n - 1}$ — the carry into the sign-bit column; $c_{n}$ — the carry out of it.
$Z$ , $C$ , $N$ , $V$ — the four flags: Zero, Carry, Negative, oVerflow.
$\oplus$ — XOR, "these two bits differ" (1 if exactly one is 1).

True or false — justify

TRUE or FALSE: If the Carry flag is set after an addition, the signed answer is definitely wrong.

FALSE. Carry only reports unsigned overflow; the signed answer can be perfectly correct. In

255 + 1

(i.e.

- 1 + 1

C = 1

but the signed result

0

is exactly right, so

V = 0

TRUE or FALSE: The Negative flag being 1 means the value stored is a negative number.

FALSE.

N

is only the copy of the MSB

r_{n - 1}

. If you are interpreting the bits as unsigned, that same set bit just means "value

\geq 2^{n - 1}

", not negative.

TRUE or FALSE: You can get signed overflow by adding a positive and a negative number.

FALSE. Adding opposite signs, the magnitude of the true sum is smaller than the larger operand, so it always stays in range. Overflow needs same-sign operands whose result-sign flips.

TRUE or FALSE: The Zero flag depends on which operation was requested.

FALSE.

Z

is computed purely from the output bits — a NOR over all of

R

. Whether it was ADD, SUB, or XOR,

Z = 1

exactly when every result bit is 0.

TRUE or FALSE: For a logic op like AND, the Carry flag reports whether the operands overlapped in high bits.

FALSE. AND/OR/XOR have no arithmetic carry chain, so most ISAs simply clear

C

(and

V

). Carry is meaningless for bitwise logic; only

Z

and

N

carry information.

TRUE or FALSE: On subtraction, Carry set (

C = 1

) signals that a borrow happened.

FALSE (ARM/x86 convention). Because

A - B = A + (\sim B) + 1

, a carry-out means no borrow, i.e.

A \geq B

C = 0

is the borrow case (

A < B

TRUE or FALSE: Overflow can occur when both operands are zero.

FALSE.

0 + 0 = 0

keeps its sign (non-negative in, non-negative out), and

0 - 0 = 0

; the sign never flips, so

V = 0

. Zero is a degenerate, always-safe case.

TRUE or FALSE: If

N = 1

and

V = 0

after a signed add, the true signed result really is negative.

TRUE. With no overflow, the sign bit is trustworthy, so

N = 1

means the correct signed answer is negative. The catch is only when

V = 1

, where

N

has been corrupted by the wrap-around.

TRUE or FALSE: Two 8-bit inputs can produce

C = 1

and

V = 1

simultaneously.

TRUE. Add two large negatives, e.g.

- 128 + (- 1) = 10000000 + 11111111

: this both wraps signed (neg+neg→"pos",

V = 1

) and carries out of the MSB (

C = 1

C

and

V

are independent, so all four combinations exist.

Spot the error

Find the flaw: "To check if unsigned

A \geq B

, branch on the Overflow flag

V

Wrong flag. Unsigned comparisons use the Carry flag (

A \geq B ⟺ C = 1

after SUB).

V

answers a signed question and would give wrong branches for unsigned data — see Signed vs Unsigned Comparison Instructions.

Find the flaw: "Overflow is

c_{n}

, the carry out of the top adder."

Overflow is

c_{n} \oplus c_{n - 1}

, the disagreement between the carry out of and the carry into the sign bit — not

c_{n}

alone. Using

c_{n}

alone would confuse it with the Carry flag.

Find the flaw: "The ALU stores the flags from the last op, so it must contain memory."

The ALU itself is combinational (no memory); the flags are latched into a separate status register, which is the sequential part. Don't attribute the register's memory to the ALU — see Combinational vs Sequential Logic.

Find the flaw: "

Z = 1

therefore no overflow happened, since a zero result is safe."

Independent conditions.

- 128 + (- 128)

in 8 bits gives

00000000

(

Z = 1

) yet

V = 1

, because the true answer

- 256

is far out of range.

Z

says nothing about whether the value is correct.

Find the flaw: "Negating

B

for subtraction is just inverting its bits:

A - B = A + \sim B

Missing the

+ 1

\sim B

is only the ones' complement; two's complement needs

A + \sim B + 1

, and that

+ 1

is supplied as carry-in = 1 to the adder. Without it you compute

A - B - 1

Find the flaw: "For a left shift, the Carry flag is set from the MSB of the input, so it just copies the sign."

Carry captures the bit shifted out of the top — which for a left shift is the old MSB, but the point is it is the departing bit that would be lost, enabling multi-word shifts to chain. Calling it "copies the sign" hides its role of preserving the spilled bit.

Why questions

WHY does the same adder circuit handle both addition and subtraction?

Two's complement makes

- B

equal

\sim B + 1

, so

A - B

becomes an ordinary addition

A + \sim B + 1

. One adder plus an invert-and-carry-in switch does both — the reason two's complement was chosen at all.

WHY is overflow defined as

c_{n} \oplus c_{n - 1}

rather than by looking at the result alone?

The sign bit gets used up holding the answer's top bit, so after the fact you can't tell a valid negative from a wrapped positive. Watching whether the carry passing into and out of the sign column agree catches the corruption at the moment it happens.

WHY can you never overflow (signed) when adding numbers of opposite sign?

The result lies strictly between the two operands' values, so its magnitude can't exceed the larger operand, which was already in range. Overflow requires pushing past a boundary, and opposite signs pull inward, not outward.

WHY does the Carry flag mean "NOT borrow" on subtraction?

Because subtraction is implemented as

A + \sim B + 1

: a carry-out of the top means the addition completed without needing to borrow from beyond the MSB, i.e.

A \geq B

. No carry-out means a borrow was needed,

A < B

WHY do ISAs bother computing

N

separately when it is "just" the MSB wire?

So conditional-branch logic has a ready-made signed-sign signal without re-deriving it. It costs almost nothing (one wire), and combined with

V

it lets a single flag test decide signed comparisons — the plumbing for Condition Codes and Conditional Branches.

WHY is the Zero flag built as a NOR over all result bits and not, say, an AND?

We want

Z = 1

only when every bit is 0. OR-ing the bits gives 1 if any bit is set, so NOT-of-OR (NOR) gives 1 exactly for the all-zeros pattern. An AND would instead detect the all-ones pattern.

Edge cases

EDGE CASE: What are the flags for

0 - 0

(8-bit)?

R = 0

Z = 1

; MSB is 0 so

N = 0

; no borrow since

A \geq B

C = 1

; no sign flip so

V = 0

. The "

C = 1

on equal" surprises people but it correctly means

A \geq B

EDGE CASE: Add the most negative number to itself:

- 128 + (- 128)

in 8 bits.

10000000 + 10000000 = 100000000

, keep 8 bits →

R = 0

. So

Z = 1

N = 0

C = 1

, and

V = 1

(neg+neg gave "non-negative"): a case where

Z

C

, and

V

are all set at once.

EDGE CASE: Negating the most negative number,

- (- 128)

, in 8 bits.

\sim (10000000) + 1 = 01111111 + 1 = 10000000 = - 128

again — it's its own negative. The magnitude

128

can't be represented, so this signed negation overflows (

V = 1

); it's the one asymmetric point of two's complement.

EDGE CASE: What does

C

report when you add

0 + 0

C = 0

: nothing spilled past the MSB, unsigned

0 + 0 = 0

fits trivially. This is the boundary that shows Carry tracks unsigned overflow, and zero can never trigger it on addition.

EDGE CASE: Largest unsigned add that does NOT set Carry, in 8 bits.

Any pair whose unsigned sum is

\leq 255

, e.g.

200 + 55 = 255 = 11111111

C = 0

(it just fits), but note

N = 1

because the MSB is set — a reminder

N

is meaningless under an unsigned interpretation.

EDGE CASE: For AND/OR/XOR, can the Overflow flag ever be 1?

No. There is no arithmetic sign to overflow, so ISAs force

V = 0

(and usually

C = 0

) for logic ops. Only

Z

and

N

are derived from the result bits.

Recall One-line survival summary

$C$ = unsigned-too-big / not-borrow; $V$ = signed-sign-flipped ( $c_{n} \oplus c_{n - 1}$ ); $N$ = MSB (meaningful only when signed); $Z$ = all-bits-zero (NOR). $C$ and $V$ are independent — any of the four combos can appear.

Connections

Parent topic
Two's Complement Representation
Full Adder and Ripple-Carry Adder
Condition Codes and Conditional Branches
Status / Flags Register (PSR / EFLAGS)
Signed vs Unsigned Comparison Instructions
Combinational vs Sequential Logic