ALU — operations, flags (zero, carry, overflow, negative): Exercises

Quick reminder of the four flags before we start (each is one bit, either 0 or 1):

Here $c_{n - 1}$ is the carry that flows into the top bit (bit 7), and $c_{n}$ is the carry that flows out of bit 7. The picture below fixes these two carries in your head — every overflow question comes back to it.

Figure — ALU — operations, flags (zero, carry, overflow, negative)

Level 1 — Recognition

Exercise 1.1 (L1)

An 8-bit ADD produces result $R = 00000000$ with carry-out $= 1$ . State Z, N, C.

Recall Solution 1.1

Z: result is all zeros $\Rightarrow$ ==Z = 1==.
N: MSB (bit 7) of $00000000$ is $0$ $\Rightarrow$ ==N = 0==.
C: we are told carry-out $= 1$ $\Rightarrow$ ==C = 1==. WHAT this looks like: this is exactly $255 + 1$ (unsigned wrap to 0). The result is zero, but a carry escaped the top — Z and C are answering two different questions.

Exercise 1.2 (L1)

An ADD gives $R = 10101100$ . Read off N and Z directly (no arithmetic needed).

Recall Solution 1.2

N = MSB = leftmost bit = $1$ $\Rightarrow$ ==N = 1==.
Z: some bits are 1, so the result is not all-zero $\Rightarrow$ ==Z = 0==. WHY no arithmetic: N is literally a wire from bit 7; Z is a NOR over all bits. Neither needs to know the operands.

Level 2 — Application

Exercise 2.1 (L2)

8-bit ADD: $A = 01100100 (100)$ , $B = 00110010 (50)$ . Find $R$ and all four flags.

Recall Solution 2.1

Add the bits: $01100100 + 00110010 = 10010110$ .

R $= 10010110 = 15 0_{u}$ . Check: $100 + 50 = 150$ . ✓
Z: not zero $\Rightarrow$ Z = 0.
N: MSB $= 1 \Rightarrow$ N = 1.
C: carry out of bit 7? $150 < 256$ , so no $\Rightarrow$ C = 0.
V: operands are pos+pos ( $a = 0, b = 0$ ) but result MSB is $1$ (looks negative). Sign flipped $\Rightarrow$ V = 1. WHY V = 1 here: signed, $100 + 50 = 150$ but the max signed value is $127$ . $150$ wrapped to $150 - 256 = - 106$ , which is exactly what $10010110$ means signed. Two positives gave a "negative" — signed overflow.

Exercise 2.2 (L2)

8-bit ADD: $A = 10000000 (- 128)$ , $B = 10000000 (- 128)$ . Find $R$ and flags.

Recall Solution 2.2

$10000000 + 10000000 = 100000000$ ; keep 8 bits $\Rightarrow R = 00000000$ .

R $= 00000000$ .
Z: all zeros $\Rightarrow$ Z = 1.
N: MSB $= 0 \Rightarrow$ N = 0.
C: carry out of bit 7 $= 1 \Rightarrow$ C = 1.
V: signs neg+neg ( $a = 1, b = 1$ ) but result sign is $0$ (positive). Flip $\Rightarrow$ V = 1. WHY: signed, $- 128 + (- 128) = - 256$ , far below $- 128$ . The signed answer is nonsense; V flags it. Notice C = 1 and V = 1 here — both fired.

Level 3 — Analysis

Exercise 3.1 (L3)

Do the subtraction $A - B$ with $A = 01000000 (64)$ , $B = 01100000 (96)$ using the ALU's real method $A + (\sim B) + 1$ . Give $R$ and all flags, and state the unsigned comparison result of $A$ vs $B$ from the carry flag.

Recall Solution 3.1

Step 1 — invert B: $\sim B = 10011111$ . Step 2 — add with carry-in 1: $01000000 + 10011111 + 1 = 11100000.$

R $= 11100000$ . Signed value: invert-and-add-1 gives $00011111 + 1 = 00100000 = 32$ , so $R = - 32$ . Check: $64 - 96 = - 32$ . ✓
Z: not zero $\Rightarrow$ Z = 0.
N: MSB $= 1 \Rightarrow$ N = 1.
C: carry out of bit 7? The top bits $0 + 1 + (carry-in from bit 6)$ … the full sum $01000000 + 10011111 + 1 = 11100000$ produced no carry out of bit 7 $\Rightarrow$ C = 0. On subtract, C = 0 means a borrow happened, i.e. $A < B$ . Indeed $64 < 96$ . ✓
V: signs of the addition $A + (\sim B)$ : $A$ positive, $\sim B$ has MSB 1 (negative). Opposite signs can never overflow $\Rightarrow$ V = 0. Unsigned comparison: C = 0 on subtract $\Rightarrow A < B$ (unsigned). $64 < 96$ . ✓

Exercise 3.2 (L3)

Same method: $A - B$ with $A = 11111111 (25 5_{u} = - 1_{s})$ , $B = 00000001 (1)$ . Find $R$ , flags, and both the unsigned and signed interpretation.

Recall Solution 3.2

$\sim B = 11111110$ . Add with carry-in 1: $11111111 + 11111110 + 1 = 111111110,$ keep 8 bits $\Rightarrow R = 11111110$ .

R $= 11111110$ . Unsigned: $255 - 1 = 254$ ; and $11111110 = 25 4_{u}$ . ✓ Signed: $- 1 - 1 = - 2$ ; and $11111110 = - 2_{s}$ . ✓ (Same bits serve both readings.)
Z: not zero $\Rightarrow$ Z = 0.
N: MSB $= 1 \Rightarrow$ N = 1.
C: carry out of bit 7 $= 1 \Rightarrow$ C = 1 $\Rightarrow$ no borrow $\Rightarrow A \geq B$ unsigned. $255 \geq 1$ . ✓
V: $A$ MSB 1 (neg), $\sim B$ MSB 1 (neg)… wait, both operands of the add are negative but the result MSB is 1 (still negative) — no sign flip $\Rightarrow$ V = 0. Signed $- 2$ is in range, correct.

Level 4 — Synthesis

Exercise 4.1 (L4)

You need to branch when signed $A > B$ . After computing $A - B$ , which combination of flags implements signed strictly-greater-than? Derive it and test on $A = 5$ , $B = 3$ and on $A = - 100$ , $B = 100$ .

Recall Solution 4.1

Derivation. Signed $A > B ⟺ A - B > 0$ . "Greater than zero" as flags: the result must be (a) not zero and (b) have the correct sign (positive). "Correct sign positive" is $N = V$ read together: the true sign of $A - B$ is $N \oplus V$ (N is the stored sign, V says whether it lied). So: $A \geq B (signed) ⟺ N \oplus V = 0 ⟺ N = V,$ and strict $A > B$ adds "not equal", i.e. Z = 0: $A > B (signed) ⟺ (N = V) AND Z = 0.$ This is exactly the ARM condition GT. See Condition Codes and Conditional Branches.

Test 1: $A = 5, B = 3$ . $A - B = 2 = 00000010$ . N = 0, V = 0 (in range), Z = 0. $N = V$ ✓ and Z = 0 ✓ $\Rightarrow$ branch taken. Correct: $5 > 3$ . ✓

Test 2: $A = - 100, B = 100$ . $A - B = - 200$ , out of signed range $\Rightarrow$ overflow. Bits: $- 100 = 10011100$ , $\sim (01100100) + 1$ : $\sim B = 10011011$ , add carry-in 1: $10011100 + 10011011 + 1 = 100111000 \Rightarrow R = 00111000 = 56$ . N = 0, but V = 1 (opposite signs $-$ became add of two negatives? let's read the add $A + \sim B$ : both MSB 1, result MSB 0 → sign flip → V = 1). So N = 0, V = 1 $\Rightarrow N \neq = V \Rightarrow$ signed $A < B$ , branch not taken. Correct: $- 100 > 100$ is false. ✓ (Notice: the stored result 56 looks positive, but V corrects that lie.)

Exercise 4.2 (L4)

Design the flag settings for a logical AND $R = A \land B$ on typical ISAs, and explain why C and V are cleared. Apply to $A = 11001100$ , $B = 10101010$ .

Recall Solution 4.2

$R = A \land B$ : bitwise AND $\Rightarrow 10001000$ .

Z: $10001000 \neq = 0 \Rightarrow$ Z = 0.
N: MSB $= 1 \Rightarrow$ N = 1.
C = 0, V = 0. WHY: AND is not arithmetic — there is no carry chain and no notion of "exceeding a numeric range". Carry and overflow only mean something for add/subtract, so ISAs define them as cleared (0) for logic ops to keep behaviour well-defined. See Combinational vs Sequential Logic for why the ALU can produce these in one pass.

Level 5 — Mastery

Exercise 5.1 (L5)

An 8-bit ADD reports flags $Z = 0, N = 0, C = 1, V = 1$ . Reconstruct one possible pair of signed operands and their true signed sum, and explain what the stored result's sign tells you (and why it's misleading).

Recall Solution 5.1

Decode the flags. V = 1 with a positive-looking result (N = 0) means neg + neg $\to$ positive (the only way a positive stored sign can overflow). C = 1 is consistent with adding two large-magnitude negatives (their unsigned patterns are big). Z = 0 means non-zero result. Construct an example: $A = 10000001 (- 127)$ , $B = 11111111 (- 1)$ . $10000001 + 11111111 = 110000000 \Rightarrow R = 1000 0000.$ Hmm, that gives $R$ MSB = 1 (N = 1) — not our target. Try $A = 10000000 (- 128)$ , $B = 10000001 (- 127)$ : $10000000 + 10000001 = 100000001 \Rightarrow R = 0000 0001.$

R $= 00000001$ : N = 0 ✓, Z = 0 ✓.
C: carry out of bit 7 = 1 ✓.
V: neg + neg → result sign 0 → flip → V = 1 ✓. True signed sum: $- 128 + (- 127) = - 255$ , which is far below $- 128$ (overflow). The stored result $00000001 = + 1$ looks positive but is completely wrong — that's precisely what V = 1 warns you about. The stored sign is meaningless after signed overflow.

Exercise 5.2 (L5)

On a CPU whose subtract sets C = NOT borrow, prove that the unsigned branch "A < B" is taken exactly when C = 0 after CMP A, B (which computes $A - B$ and discards the result). Then verify with $A = 3, B = 5$ and $A = 200, B = 50$ .

Recall Solution 5.2

Proof. CMP computes $A + (\sim B) + 1$ . The carry-out of this 9-bit sum is $c_{8}$ . Unsigned, $A + (\sim B) + 1 = A + (2^{8} - 1 - B) + 1 = 2^{8} + (A - B)$ . If $A \geq B$ then $A - B \geq 0$ , so the sum $\geq 2^{8}$ , producing carry-out $c_{8} = 1$ (C = 1, no borrow). If $A < B$ then $A - B < 0$ , so the sum $< 2^{8}$ , giving $c_{8} = 0$ (C = 0, borrow occurred). Therefore: $C = 0 ⟺ A < B (unsigned) . ■$ Test 1: $A = 3, B = 5$ . $\sim B = 11111010$ ; $00000011 + 11111010 + 1 = 11111110$ , no carry-out $\Rightarrow$ C = 0 $\Rightarrow A < B$ . True: $3 < 5$ . ✓ Test 2: $A = 200, B = 50$ . $\sim (00110010) = 11001101$ ; $11001000 + 11001101 + 1 = 110010110$ , carry-out = 1 $\Rightarrow$ C = 1 $\Rightarrow$ not ( $A < B$ ). True: $200 \neq < 50$ . ✓

Recall One-line self-test

After CMP A, B (i.e. $A - B$ ): unsigned A < B is ::: C = 0; signed A < B is ::: N ≠ V; equal is ::: Z = 1.

Connections

Parent: 4.1.06 ALU — operations, flags (zero, carry, overflow, negative) (Hinglish)
Two's Complement Representation
Full Adder and Ripple-Carry Adder
Condition Codes and Conditional Branches
Status / Flags Register (PSR / EFLAGS)
Signed vs Unsigned Comparison Instructions
Combinational vs Sequential Logic