Registers — general purpose, special (PC, SP, LR, CPSR): Question bank

Definition Terms this page uses before the questions

CPSR = Current Program Status Register, the special register holding the N/Z/C/V condition flags (and mode bits).
LIFO = Last-In-First-Out: the most recently pushed item is the first one popped — like a stack of plates.
Full-descending stack: a stack that ==grows toward lower addresses==, with SP pointing at the last item pushed (the occupied top). "Descending" = each push lowers the address; "full" = SP sits on data, not on the next free slot.
Register width assumption: every $\pm 4$ below assumes a 32-bit ARM machine, where one word (and one register) is $4$ bytes. On a 64-bit machine the step would be $8$ .
Relative-branch symbols (used in one item): $P C_{ref}$ = the reference PC value the offset is measured from; $L$ = instruction length in bytes ( $L = 4$ on 32-bit ARM); $o$ = the signed offset counted in instructions.

True or false — justify

A register is just a very small, very fast region of RAM.

False — a register lives on the CPU silicon wired straight to the ALU and is named (e.g. R4), not addressed by a memory address; RAM is off the datapath and reached via Addressing Modes.

A 32-bit register can hold exactly

32

different values.

False — it holds

2^{32} \approx 4.29 \times 1 0^{9}

values; the

32

is the number of bits, and

W

bits give

2^{W}

combinations.

CMP a, b stores its subtraction result in a register.

False — CMP computes

a - b

only to set the N/Z/C/V flags in CPSR (Current Program Status Register) and then throws the numeric result away; that is the whole point of a compare.

After a perfectly balanced sequence of pushes and pops, SP holds the same value it started with.

True — on a 32-bit ARM each PUSH does

S P - = 4

and each matching POP does

S P + = 4

, so a balanced run nets zero and the stack is self-cleaning (LIFO, last-in-first-out).

On classic ARM, reading PC gives you the address of the instruction currently executing.

False — because the pipeline fetches ahead, PC reads as current + 8; the hardware already advanced it before this instruction runs.

BL target saves the current PC into LR.

False — it saves

P C_{next}

(the instruction after the call). Saving the call itself would make BX LR re-execute the call forever.

A leaf function that calls no one can safely return using only BX LR.

True — nothing overwrites LR inside a leaf, so the return address set by BL survives untouched; only non-leaf functions must spill LR to the stack.

The Z flag being set means the result was negative.

False — Z=1 means the result was all zeros; the N flag (result MSB=1) reports negative.

Carry (C) and signed Overflow (V) always agree.

False — C is about unsigned wrap/borrow (carry out of the top bit), V is about signed range in Two's Complement Arithmetic; e.g. 0x7F+0x01 gives C=0 but V=1.

General-purpose registers have no hardware-imposed meaning at all.

Mostly true, but note some "GPRs" are conventionally reserved by the calling convention (e.g. as SP/LR), so the hardware stays neutral while software pins meaning.

Spot the error

A student writes PUSH as: "store Mem[SP]=v, then SP -= 4."

Wrong order for a full-descending stack (one that grows toward lower addresses) — you must decrement first (

S P - = 4

) so you don't overwrite the item currently at the top before making room.

"To POP, do SP += 4 then read Mem[SP]."

Wrong — you read before freeing the slot. Bumping SP first makes you read the wrong location and hands a live slot back to the allocator prematurely.

Function A calls B; the compiler leaves A's return address only in LR and never touches the stack.

The BL into B overwrites LR with B's return address, destroying A's — A must PUSH {LR} on entry and POP {PC} on exit for unlimited nesting.

"A relative branch does PC ← PC + o where o is the offset in bytes counted in words."

Confused units — recall

P C_{ref}

is the reference PC,

L

the instruction length in bytes, and

o

the offset in instructions; the branch scales the offset:

P C \leftarrow P C_{ref} + L \cdot o

with

L = 4

bytes on 32-bit ARM.

"POP {R4, LR} then BX LR is the fastest way to return."

It works but wastes an instruction — POP {R4, PC} loads the saved return address straight into PC, returning in one step.

"CMP sets flags, so after it R0 changes."

CMP never writes a general-purpose register; only CPSR's flags change. Confusing it with SUBS (which sets flags and stores) is the trap.

Why questions

Why must the PC be incremented before the current instruction executes, not after?

So that by execute time PC already names the following instruction — this makes BL's "save

P C_{next}

" and default sequential flow fall out for free (see Instruction Cycle (Fetch-Decode-Execute)).

Why do registers exist at all instead of just using cache?

The ALU produces a result in ~1 cycle, but even cache costs several; registers sit on the ALU's datapath at zero extra latency, so the hottest operands live there.

Why does signed overflow (V) require both operands to share a sign?

If two positives are added, the true sum can only exceed the top of the representable range; a same-sign pair whose result flips sign is the only way

a + b

can leave

[- 2^{n - 1}, 2^{n - 1} - 1]

— opposite signs can never overflow.

Why does BEQ after CMP a,b correctly branch when

a = b

CMP computes

a - b

; equality makes that zero, setting Z=1, and BEQ branches exactly on Z=1 — the logic is first-principles airtight.

Why is a full-descending stack said to grow "downward"?

Each PUSH decreases SP toward lower addresses, so successive items occupy smaller and smaller addresses — the "top" of the stack is the lowest used address.

Why can't the compiler keep every variable in a register?

There are only a handful of GPRs; register allocation keeps the hottest variables in them and spills the rest to the stack, trading register scarcity against RAM latency.

Edge cases

What N/Z/C/V results from an 8-bit 0x80 + 0x80?

- 128 + - 128

: result bits

= 0 x 00

so Z=1, N=0, carry out gives C=1, and neg+neg→positive means V=1 (signed overflow of two negatives).

What does the C flag do on an unsigned subtraction underflow, e.g. 8-bit CMP 0x00, 0x01 (computing

0 - 1

On ARM, subtraction sets C as NOT-borrow:

0 - 1

underflows (borrow needed), so C=0, while the result bits

= 0 x F F

give N=1 and Z=0 — this borrow behavior is what BLO/BHS (unsigned branches) read.

What is CPSR after a result of exactly zero?

Z=1 and N=0 always (all-zero has MSB 0); C and V depend on the operation, not on the result being zero.

A recursion 1000 levels deep — where do the 1000 return addresses live?

On the stack, not in LR — each frame's PUSH {LR} spills its own return address, so the single LR only ever holds the current frame's, while SP walks the chain.

What happens to SP if a function pushes but forgets to pop before returning?

SP is left decremented (stack "leaks"), the return likely reads a garbage address, and the calling convention is violated — a classic stack-corruption bug.

Can V be set when adding a positive and a negative number?

No — opposite-sign addition always lands inside the representable range, so V=0; overflow needs matching operand signs.

Recall One-line summary of the traps

Order matters (push/pop, PC-before-execute), LR is only the current frame's return address, CMP writes flags not registers, and C≠V because unsigned wrap and signed overflow are different questions.