ISA (Instruction Set Architecture) — RISC vs CISC

4.1.3 · Coding › Computer Architecture (Deep)

Intuition The 80/20 core idea

ISA ek contract hai hardware aur software ke beech mein. Yeh kehta hai: "Yeh rahe woh instructions jo main (CPU) samajhne ka waada karta hoon, woh registers jo tum use kar sakte ho, aur memory tumhe kaisi dikhti hai." Compiler/assembler is contract ke hisaab se likhta hai; silicon usse implement karta hai. RISC vs CISC ek design philosophy ki bahas hai ki har instruction kitna bada aur fancy hona chahiye.

CISC (Complex): kam-instruction wale programs, har instruction bahut ZYADA kaam karta hai (memory-to-memory math bhi). Hardware complicated hota hai.
RISC (Reduced): bahut saari simple instructions, har ek SIRF EK chhoti cheez fast karti hai. Hardware simple hota hai, compiler zyada mehnat karta hai.

80/20: agar sirf ek line yaad rakhni ho — CISC complexity ko hardware mein pack karta hai; RISC complexity ko compiler/software mein dhakelta hai. Baaki almost saare differences usi ek choice ka consequence hain.

ISA KYA hai?

RISC vs CISC exist kyun karta hai? (historical why)

Defining feature: load/store rule

Worked example Same kaam:

mem[A] = mem[A] + mem[B] CISC (x86-style, conceptual):

ADD  A, B        ; one instruction: load A, load B, add, store to A

Yeh kaise kaam karta hai: hardware ka microcode andar se kai memory accesses aur ek add karta hai — tumse chhupa hua.

RISC (ARM/RISC-V-style):

LW   r1, A       ; load word from A into r1
LW   r2, B       ; load word from B into r2
ADD  r1, r1, r2  ; register + register
SW   r1, A       ; store r1 back to A

Yeh kaise kaam karta hai: har instruction ek chhota well-defined step hai → pipeline, decode, aur time karna aasaan. Yeh step (pehle LWs) kyun? Kyunki load/store ISA mein ek ADD ko memory touch karna forbidden hai; humein data ko registers mein stage karna hoga.

Figure — ISA (Instruction Set Architecture) — RISC vs CISC

Trade-off, precisely (derivation, dump nahi)

Worked example Iron Law ke saath Forecast-then-Verify

Ek loop do tarah compile ki gayi hai. Pehle forecast karo kaun faster hai, phir calculate karo.

Design	$I C$	$C P I$	$T_{cy c l e}$
CISC	8 instr	5 cyc	0.5 ns
RISC	16 instr	1.2 cyc	0.4 ns

Forecast: RISC ke paas 2× instructions hain lekin tiny CPI aur faster clock hai — guess hai ki RISC jeetta hai. Verify:

CISC: $T = 8 \times 5 \times 0.5 = 20$ ns.
RISC: $T = 16 \times 1.2 \times 0.4 = 7.68$ ns. Kyun: bhale hi $I C$ double hua, $C P I$ ~4× giraa aur clock faster hui — product chhota hai. RISC yahan jeetta hai. ✔ (Steel-man: agar CPI barabar hoti, toh CISC ka lower IC jeetta — isliye result workload/CPI dependent hai, nature ka koi law nahi.)

Side-by-side cheat table (active-recall friendly)

Definition RISC vs CISC at a glance

Aspect	RISC	CISC
Instruction length	Fixed (e.g. 32-bit)	Variable (1–15 bytes in x86)
Memory access	Sirf load/store ke zariye	Arithmetic memory touch kar sakti hai
Instruction count/program	Zyada	Kam
CPI	Kam (~1, pipelines achhi tarah)	Zyada (multi-cycle/microcoded)
Decode complexity	Simple, hardwired control	Complex, aksar microcoded
Registers	Zyada (e.g. 16–32)	Historically kam
Complexity kahan rehti hai	Compiler / software	Hardware
Examples	ARM, RISC-V, MIPS, SPARC	x86 / x86-64, VAX, System/360

Common mistakes (Steel-manned)

Flashcards

ISA kya hai?

Woh abstract hardware–software contract: instructions, registers, addressing modes, aur data types jo ek processor software ko expose karta hai (is baat se independent ki chip physically kaise bani hai).

ISA vs microarchitecture?

ISA = visible interface/"menu" (e.g. x86-64); microarchitecture = internal implementation/"kitchen" (e.g. Intel ka vs AMD ka same ISA ka design).

RISC vs CISC mein sabse gehri ek difference?

Complexity kahan rehti hai — CISC use hardware mein dhakelta hai (fat instructions); RISC use compiler/software mein dhakelta hai (simple instructions).

Load/store architecture define karo.

Arithmetic/ALU instructions sirf registers par operate karti hain; memory sirf explicit LOAD aur STORE instructions ke zariye access hoti hai. (RISC hallmark.)

Iron Law of processor performance batao.

Time = IC × CPI × T_cycle (instruction count × cycles per instruction × clock period).

Derive karo ki Iron Law ke units kyun kaam karte hain.

(instr/prog)·(cyc/instr)·(s/cyc): instr aur cyc cancel hote hain → s/prog = total CPU time.

CISC Iron Law ka kaun sa factor reduce karta hai, aur iska kya cost hai?

IC reduce karta hai; cost hai zyada CPI aur hard-to-shrink clock period.

RISC kaun se factors favor karta hai?

Low CPI (~1 via pipelining) aur chhota T_cycle; zyada IC accept karta hai.

Fixed-length encoding RISC ko kyun help karta hai?

Uniform instructions decode aur pipeline aasaani se hoti hain → low CPI aur faster clock.

"RISC" ka common galat padhna kya hai?

Yeh sochna ki iska matlab hai ISA mein kam instructions; actually matlab hai har instruction ki reduced complexity.

Modern x86 CPUs line ko kaise blur karte hain?

Woh CISC instructions ko RISC-jaise micro-ops (µops) mein decode karte hain aur unhe RISC-style pipeline mein chalate hain — baahir CISC, andar RISC.

Do RISC ISAs aur do CISC ISAs?

RISC: ARM, RISC-V (MIPS, SPARC bhi). CISC: x86/x86-64, VAX (System/360 bhi).

Recall Feynman: ek 12-saal ke bache ko samjhao (hidden — pehle khud try karo!)

Socho ki tum ek robot ko sandwich banane ke instructions de rahe ho.

CISC robot: tum kaho "sandwich banao!" — ek badi command. Robot ke paas bahut saari built-in machinery hai saari chhoti steps figure out karne ke liye. Tumhare liye chhota, complicated robot.
RISC robot: tumhe kehna padega "bread uthao… butter lagao… cheese daalo… bread band karo." — bahut saari tiny commands. Robot simple hai aur har chhoti step super fast karta hai, lekin tum (compiler) ko zyada soochna padhta hai aur zyada bolna padhta hai. Koi "best" nahi hai — yeh depend karta hai ki tum ek clever robot chahte ho ya ek clever instructor. Aur ISA bas un words ki list hai jo robot samajhne ka waada karta hai.

Connections

Microarchitecture vs ISA — ISA ke neeche ka implementation layer.
Pipelining — kyun RISC fixed-length, single-cycle-shaped instructions chahta hai.
CPI and the Iron Law of Performance — woh equation jo trade-off quantify karti hai.
Microcode — CISC ki complex instructions internally steps mein kaise tooti jaati hain.
Compilers and Code Generation — jahan RISC apni complexity dump karta hai.
Addressing Modes — CISC ka rich set vs RISC ka minimal set.
Registers and the Register File — load/store ko kai registers kyun chahiye.
Caches and Memory Hierarchy — load/store discipline memory speed ke saath interact karta hai.