Harvard architecture — separate instruction - data memory: Worked examples

Before any symbols, let's re-earn the two we lean on the whole page.

Cell	The scenario	The "edge" it tests
A	Typical program, $0 < f < 1$	The everyday case
B	$f = 0$ (all register arithmetic)	Zero input — degenerate low
C	$f = 1$ (every instruction touches data)	Limiting high — the ceiling
D	Collision — data & fetch want the same memory	Harvard's max breaks; extra cycle appears
E	Different word widths (8-bit data, 16-bit code)	Non-speed advantage; word-size case
F	Real chip: Modified Harvard cache miss	Where the ideal model bends
G	Word problem (real workload sizing)	Translate English → $N, f$
H	Exam twist: "is Harvard always faster?"	Sign/logic trap; $S$ vs cost

Cell A — the everyday case

Worked example Example 1 — Counting cycles for a normal loop (Cell A)

A loop runs $N = 1000$ instructions; a fraction $f = 0.4$ are loads/stores. Find $T_{vN}$ , $T_{H}$ , and $S$ .

Forecast: guess before computing — will the speed-up be closer to $1 \times$ , $1.4 \times$ , or $2 \times$ ?

Von Neumann cycles. $T_{vN} = N (1 + f) = 1000 (1 + 0.4) = 1400$ . Why this step? Every one of the 1000 instructions needs its own fetch cycle, and the 400 data-touching ones each need a second cycle on the same shared bus. Costs add: $1000 + 400 = 1400$ .
Harvard cycles. $T_{H} = N = 1000$ . Why this step? The 400 data accesses run on the data bus at the same time as fetches run on the instruction bus. They cost 0 extra cycles — hidden under the fetches.
Speed-up. $S = \frac{1400}{1000} = 1.4$ . Why this step? $S$ is just "how many times longer von Neumann takes."

Verify: the formula predicts $S = 1 + f = 1 + 0.4 = 1.4$ . ✔ Matches. The forecast answer was $1.4 \times$ .

Figure — Harvard architecture — separate instruction - data memory

Cell B — the zero case (degenerate low)

Cell C — the limiting high (the ceiling)

Cell D — the collision (where max breaks)

Worked example Example 4 — When the ideal overlap fails (Cell D)

In pure Harvard the data lives in its own memory, so fetch and data never fight. But suppose a design lets a data access occasionally collide with a fetch on a shared resource (e.g. a single-port block used by both). Say $N = 1000$ , $f = 0.4$ , and a fraction $c = 0.25$ of those data accesses collide and force a 1-cycle stall.

Forecast: will Harvard's time still be exactly $N = 1000$ ?

Colliding accesses. Data accesses $= f N = 0.4 \times 1000 = 400$ . Colliding ones $= c \cdot f N = 0.25 \times 400 = 100$ . Why this step? Only the collisions cost extra; the other 300 still hide perfectly.
Harvard time with collisions. $T_{H}^{'} = N + c f N = 1000 + 100 = 1100$ . Why this step? Each collision breaks the "max" — the CPU must serialize that one access, adding a cycle. The clean 300 add nothing.
Realistic speed-up. $S^{'} = \frac{T _{vN}}{T _{H}^{'}} = \frac{1400}{1100} \approx 1.27$ . Why this step? Compare against the same von Neumann baseline ( $1400$ ).

Verify: ideal Harvard would give $1.4$ ; collisions drop it to $\approx 1.27$ . ✔ The lesson: the tidy $S = 1 + f$ assumes zero collisions. This is exactly the "when they don't collide" caveat from the parent note.

Cell E — different word widths (a non-speed win)

Worked example Example 5 — 8-bit data, 16-bit instructions (Cell E)

An 8-bit DSP stores 16-bit instructions but only 8-bit data. It runs $N = 1000$ instructions, $f = 0.3$ . Show two separate benefits.

Forecast: name a benefit that has nothing to do with the speed-up formula.

Speed benefit (as before). $S = 1 + f = 1 + 0.3 = 1.3$ . Why this step? The timing model does not care about widths — it only counts accesses.
Width benefit. Instruction memory can be 16 bits wide; data memory 8 bits wide. In von Neumann, one shared bus must pick a single width — you'd waste bits or need padding. Why this step? Separate memories are independently sized. This shrinks the chip and cuts cost.
Address benefit. The two memories can even have different address ranges (e.g. 4K of code, 256 bytes of data), each sized to need.

Verify: $S = 1.3$ ✔ for the speed part; the width/address wins are structural and are why AVR/PIC/Cortex-M chips choose Harvard-style layouts. (See also Memory bus and bandwidth.)

Cell F — Modified Harvard cache miss (where the model bends)

Worked example Example 6 — Real chip: split caches with a miss (Cell F)

A Modified-Harvard CPU has separate L1 I-cache and D-cache over one unified main memory. Suppose a load misses the D-cache and must go to main memory, costing $M = 10$ cycles. In a block of $N = 100$ instructions with $f = 0.4$ , exactly one load misses.

Forecast: does one miss ruin the whole block's timing?

Ideal Harvard part. With both caches hitting, $T_{H} = N = 100$ cycles. Why this step? Cache hits behave like pure Harvard — I-cache feeds fetches, D-cache feeds data, in parallel.
Add the miss penalty. One miss adds $M - 1 = 9$ extra stall cycles (the missing access would have cost 1; it now costs 10). Why this step? On a miss the D-cache can't overlap; the CPU waits on shared main memory — a temporary return to von Neumann behaviour.
Total. $T = 100 + 9 = 109$ cycles.

Verify: $T = 109$ ✔. One miss adds only $\approx 9%$ here — but a miss-heavy loop erodes Harvard's advantage. This is why the parent note calls Modified Harvard "best of both": fast when caches hit, gracefully falling back when they don't. (Related: Pipelining, CPU instruction cycle.)

Cell G — the word problem

Worked example Example 7 — Sizing a real workload from English (Cell G)

"A sensor firmware runs a control loop 50 times per second. Each pass executes 80 instructions, of which 24 read the sensor or write an actuator. On a Harvard chip, how many cycles per second are spent, and what is the speed-up over von Neumann?"

Forecast: first translate — what are $N$ and $f$ for one second?

Translate to $N$ . One pass = 80 instructions; 50 passes/sec $\Rightarrow N = 80 \times 50 = 4000$ instructions per second. Why this step? $N$ must cover the whole time window we're asked about (one second).
Translate to $f$ . Per pass, 24 of 80 touch data $\Rightarrow f = 24/80 = 0.3$ . Why this step? $f$ is a ratio, so it's the same per pass or per second.
Harvard cycles. $T_{H} = N = 4000$ cycles/sec.
Speed-up. $S = 1 + f = 1.3$ ; von Neumann would need $T_{vN} = 4000 \times 1.3 = 5200$ cycles/sec.

Verify: $T_{vN} = N (1 + f) = 4000 (1.3) = 5200$ ✔ and $S = 5200/4000 = 1.3$ ✔. Units check: (instructions/sec) × (cycles/instruction, here 1 baseline) = cycles/sec. ✔

Cell H — the exam twist

Worked example Example 8 — "Is Harvard always faster?" (Cell H)

Exam claim: "A Harvard machine at the same clock is always faster than von Neumann, so we should always choose it." True or false — and where does the argument break?

Forecast: find the value of $f$ where the "faster" claim collapses.

Speed side. $S = 1 + f$ . Since $f \geq 0$ , $S \geq 1$ : Harvard is never slower on this metric. So far the claim looks safe. Why this step? Establish the best case before finding the flaw.
The break. At $f = 0$ , $S = 1$ — zero advantage. So "always faster" is false; it's only "never slower," and equal when $f = 0$ . Why this step? One counterexample ( $f = 0$ ) kills an "always" claim.
The hidden cost. Harvard needs two memory systems, more pins and controllers → more silicon area and money. When $f$ is tiny, you pay that cost for ~no benefit. Why this step? "Faster" ignores the price; engineering compares benefit vs cost.

Verify: at $f = 0.05$ , $S = 1.05$ — a mere $5%$ gain for a full second memory system. ✔ Verdict: false. Harvard wins only when data traffic ( $f$ ) is high enough to justify the hardware. (This is the parent's steel-manned mistake, made quantitative.)

Recall Quick self-test across the matrix

Cell B — if $f = 0$ , what is $S$ ? ::: $1$ (no gain; nothing to overlap). Cell C — the ceiling of $S$ and why? ::: $2$ , because $f \leq 1$ so $1 + f \leq 2$ . Cell D — why does a collision add a cycle? ::: The overlap ("max") breaks; the CPU must serialize that access, +1 cycle. Cell G — 80 instr/pass, 50 passes/sec, 24 data → what are $N$ and $f$ ? ::: $N = 4000$ /sec, $f = 0.3$ . Cell H — is "Harvard always faster" true? ::: No — only "never slower"; equal at $f = 0$ , and it costs extra hardware.

Connections

Parent: Harvard architecture — the model these examples exercise.
Von Neumann architecture — the $T_{vN} = N (1 + f)$ baseline every example compares to.
Von Neumann bottleneck — why costs add on one bus (Cell A, D).
Cache memory — split I/D caches drive Cell F's Modified-Harvard numbers.
Pipelining — collisions (Cell D) are structural hazards this removes.
CPU instruction cycle — the fetch that data hides under.
Microcontrollers (AVR PIC ARM Cortex-M) — real users of Cell E's width freedom.
Memory bus and bandwidth — two buses = double effective throughput.

Worked examples — Harvard architecture — separate instruction - data memory

The scenario matrix