Question bank — Harvard architecture — separate instruction - data memory

False. It is one CPU with two memory paths. The parallelism lives in memory access (fetch + data at once), not in computation — one chef, two delivery doors.

False. The idealized gain is $S=1+f$; when $f=0$ (register-only arithmetic) $S=1$, i.e. no gain at all. Harvard only wins when there is data traffic to hide under the fetch.

True. That is the entire point — the instruction bus and data bus are physically separate wires, so two independent signals travel simultaneously.

False. Modified Harvard has one unified main memory (one address space); the split is only in the L1 I-cache and D-cache near the CPU. The programmer sees a flat, von-Neumann-like memory.

False. You only reap two buses' worth of throughput when a fetch and a data access are both ready in the same cycle. If $f$ is small the data bus sits idle most cycles, so the useful gain is $1+f$, not $2$ — double bandwidth is a peak number, not the everyday one.

False. Instruction memory is separate and usually read-only, so the CPU cannot easily write new instructions as data. This is precisely why pure Harvard is rare and Modified Harvard dominates.

False. $f$ is a fraction, so $0\le f\le 1$, which bounds $S$ between $1$ and $2$. Even if every instruction touched memory ($f=1$), the ceiling is exactly $2\times$.

False. They are Modified Harvard: unified main memory with split L1 caches. This keeps von Neumann's flexibility (load programs as data) while enjoying Harvard's parallel fetch/access on the hot path.

It conflates executing with fetching. The two buses let you fetch one instruction while accessing data for another — one execution stream, two memory operations. Executing two instructions per cycle is superscalar issue, a different mechanism.

This is only true for pure Harvard. Modified Harvard has a writable unified backing memory, so programs are loaded as ordinary data and then fetched as instructions — normal OSes and compilers run fine.

The justification is backwards. Correct reasoning, step by step: (1) von Neumann has one bus, which can carry only one addressed transaction per cycle. (2) Every one of the $N$ instructions must first be fetched, costing $N$ cycles. (3) The $fN$ load/store instructions each need a second, separate trip on that same single bus to move their data — because the bus was busy carrying the fetch, the data cannot ride along with it. (4) Those two uses therefore take turns, so their costs add: $N+fN=N(1+f)$. Simultaneity is the Harvard property (two buses), never von Neumann's.

It only removes the structural hazard where fetch and data access fight over one memory port. Data hazards (an instruction needing a result not yet computed) and control hazards (branches) are unaffected — those live in Pipelining, not the memory buses.

Sharing a chip is not sharing a bus. Because Harvard has separate memories, instruction memory can be 16-bit wide while data memory is 8-bit wide. Independent widths are a feature of the separation, not a limitation.

One shared bus serializes fetch and data, so their per-cycle costs are sequential and sum: $N+fN$. Two independent buses run concurrently, so the smaller cost (data) hides under the larger (fetch) — you pay the maximum of the two, which is $N$.

With no loads/stores there is nothing for the data bus to carry, so the second bus sits idle every cycle. There is no work to overlap, hence $S=1+0=1$.

Besides the fetch/data overlap, separate memories allow different word widths and address sizes (e.g. wide instruction ROM, narrow data RAM), giving tighter, cheaper silicon — which is why AVR, PIC and ARM Cortex-M are Modified Harvard.

Because underneath the caches there is a single unified main memory (the von Neumann part). Only the fast L1 layer near the CPU is split, so it is a hybrid — Harvard behaviour on top of a von Neumann memory.

A wider single bus still carries one addressed transaction at a time; you can move more bits per trip but still choose fetch or data each cycle. Harvard's win is issuing two distinct addresses (one instruction address, one data address) in the same cycle, which one bus cannot do.

Because typical programs have $f\approx 0.3$–$0.4$: only about a third of instructions are loads/stores, the rest are register-only. Since $S=1+f$, that measured $f$ pins the gain to $1.3$–$1.4$.

$S=1+0=1$: no speed-up, and the extra data memory, pins and controller are wasted hardware. Harvard is a loss here in cost terms.

This is the best case, $S=1+1=2$. Every fetch is perfectly shadowed by a data access, so Harvard runs twice as fast as the equivalent von Neumann machine.

No. On a data-cache miss the access falls through to the shared backing memory, reintroducing the von Neumann bottleneck for that access — the parallelism guarantee holds only while both operations hit their separate L1 caches.

Yes, symmetrically. An instruction-cache miss must go fetch the instruction from the same unified main memory the data path uses, so it too serializes against any concurrent data access — the split-cache parallelism is only free while both the I-cache and D-cache hit.

No. The overlap in the model is fetch (instruction bus) versus data (data bus), not data versus data. Two data accesses still contend for the single data bus and take turns, so they do not both hide for free.

Nothing collides, because pure Harvard has separate memories with separate address spaces — address $0$ in instruction memory and address $0$ in data memory are different physical cells. This is exactly why loading code as data is awkward.

Not directly. A no-data instruction has nothing for the data bus to carry that cycle, so its own execution sees $S=1$; the aggregate program speed-up still averages to $1+f$ over the whole instruction mix.