Foundations — Harvard architecture — separate instruction - data memory

This page assumes you know nothing. Every word, symbol, and picture the parent note leans on is built here from the floor up, in an order where each idea only uses ideas already defined.

0. The two things a computer moves around

Before any architecture makes sense, you must see that a running program is made of exactly two kinds of information, and telling them apart is the whole game.

Figure 1 — recipe vs ingredient: the two information streams that reach the CPU.

WHY the topic needs this: Harvard architecture only matters because these two kinds of information travel to the CPU. As shown in Figure 1, the blue "recipe" stream and the orange "ingredient" stream both feed one chef. If you can't picture "recipe vs ingredient" as two distinct streams, the phrase "separate instruction/data memory" is meaningless. Everything below is about how these two streams reach the worker.

1. The CPU — the worker

The key fact we will lean on later: there is one chef. Not two. When we say Harvard is "parallel," the parallelism is in the deliveries, never in a second chef. (This is the #1 misconception the parent note warns about — we defuse it now, before the symbol ever appears.)

2. Memory — the storeroom

3. The bus — the delivery pipe

This is the single most important word on the whole topic, so we define it before it ever appears in a formula.

Figure 2 — a bus is a hallway: only one item crosses per tick, so a second item must wait for the next tick.

WHY the topic needs this: the entire Harvard-vs-von-Neumann argument is "how many hallways?" As shown in Figure 2, one hallway forces recipes and ingredients to take turns — the green item goes this tick, the other waits. Two hallways let them travel at once. Every later sentence about "separate buses" is really about this picture.

4. The clock and the cycle — the heartbeat

Now we can define time. Speed comparisons need a unit of time, and for a CPU that unit is the cycle.

5. The instruction cycle — fetch, decode, execute

The topic's central tension in one line: fetch and data access are two separate errands. Do they share a hallway (take turns) or get one each (go together)?

6. The two rival organizations — named at last

Only now that "chef", "pantry", "hallway", "tick", "fetch", "data access" all mean something can we name the two designs.

Figure 3 — the two rival organizations side by side: one hallway (take turns) vs two hallways (both at once).

As shown in Figure 3 (left), von Neumann's single blue bus is the sole path shared by both memories, so it can only serve one errand per tick. On the right, Harvard's blue instruction bus and orange data bus run independently.

7. The symbols in the speed-up formula

The parent's headline result is $S=1+f$. We now define every symbol from zero, then derive the formula line by line.

Figure 4 — $f=0.4$ of $N=10$ instructions: 4 orange bars touch data, 6 blue bars stay in registers.

As shown in Figure 4, $f\cdot N=0.4\times 10=4$ instructions need an ingredient trip; the rest are register-only.

The two time symbols — defined before they enter $S$

Neither is a bare word — each has an explicit formula, which we build now.

Deriving $T_{\text{vN}}$ (one hallway → costs ADD)

WHAT we do: count every tick the single bus must spend. WHY: on one hallway a fetch and a data access can never share a tick, so their costs add. WHAT IT LOOKS LIKE: Figure 3 (left) — everything squeezes through one blue bus.

• Every one of the $N$ instructions needs its own fetch tick → $N$ ticks.
• The $f\cdot N$ data-touching instructions each need one more tick on that same bus → $fN$ ticks.

$T_{\text{vN}}=\underset{\text{fetches}}{\underbrace{N}}+\underset{\text{data turns}}{\underbrace{fN}}=N(1+f)$

Deriving $T_{\text{H}}$ (two hallways → costs OVERLAP)

WHAT we do: count ticks when fetch and data ride separate buses. WHY: with two hallways the data access happens inside the same tick as the fetch, so costs don't add — they overlap (we take the max, not the sum). WHAT IT LOOKS LIKE: Figure 3 (right) — blue and orange buses fire in the same tick.

• The $N$ fetches run on the instruction bus → $N$ ticks.
• The $fN$ data accesses hide under those fetches on the data bus → $0$ extra ticks.

$T_{\text{H}}=\max (N,fN)=N(\text{since }f\le 1)$

Putting them into $S$ and cancelling

Now substitute the two formulae we just derived and cancel the common factor $N$:

$S=\frac{T_{\text{vN}}}{T_{\text{H}}}=\frac{N(1+f)}{N}=\frac{\cancel{N}(1+f)}{\cancel{N}}=1+f$

8. Cache and Modified Harvard — needed for real chips

Prerequisite map

Every arrow below names a relationship stated in the text: "Instruction" and "Data" are the two streams (§0) that create the "Fetch / Data access" errands (§5); those errands force the "Von Neumann one hallway" vs "Harvard two hallways" choice (§6); each design gives a time formula ($T_{\text{vN}}$, $T_{\text{H}}$), which combine with the count $N$ and fraction $f$ into $S=1+f$ (§7). "Cache" is defined from "Memory" (§8) and "Modified Harvard" builds on both "Harvard" and "Cache" (§8).

Equipment checklist

Cover the right side. If you can answer each, you are ready for the parent note.

Connections

• Harvard architecture (parent topic) — where these foundations get used to derive $S=1+f$.
• Von Neumann architecture — the one-hallway design defined here.
• Von Neumann bottleneck — the take-turns slowdown these symbols quantify.
• CPU instruction cycle — where "fetch" lives in the fetch/decode/execute loop.
• Cache memory — the "shelf on the counter" behind Modified Harvard.
• Memory bus and bandwidth — deeper on what "one item per bus per cycle" means.
• Pipelining — another way overlapping errands buys speed.
• Microcontrollers (AVR PIC ARM Cortex-M) — real chips built on these ideas.