Visual walkthrough — RISC-V custom extensions for accelerators

6.5.11 · D2 · Hardware › Advanced & Emerging Architectures › RISC-V custom extensions for accelerators

Yeh 6.5.11 RISC-V custom extensions for accelerators (Hinglish) aur uske English parent ka picture-first companion hai. Agar koi word naya lage, hum use pehle build karte hain, phir use karte hain.

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Step 1 — Instruction hoti kya hai? 32 light switches ki ek row

KYA HAI. Ek single RISC-V instruction kuch aur nahi balki 32 binary digits ka ek fixed group hai — 32 chote switches, har ek ya toh OFF ($0$) ya ON ($1$). Hum inhe right se number karte hain: bit $0$ bilkul right mein hai, bit $31$ bilkul left mein. Notation $\text{inst[6:0]}$ ka matlab sirf itna hai "switches number 0 se 6 tak" — saath sabse right wale switches.

KYUN. Isse pehle ki hum "opcode space" ya "fields" ki baat karein, humein yeh agree karna hoga ki ek instruction fixed positions wali physical row of switches hai. Iske baad ki har idea bas us row ko labelled zones mein todna hai. Agar row ki width fixed na hoti, toh koi bhi accounting kaam nahi karti.

PICTURE. Neeche: 32-switch row. Right side ke saath orange switches woh zone hain jo decide karte hain ki yeh instruction kaunsi family se hai.

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Step 2 — Opcode: 7 switches jo family ka naam batate hain

KYA HAI. Lowest 7 bits, $\text{inst[6:0]}$, opcode hain. Saath switches $2^7=128$ alag patterns dikha sakte hain, isliye zyada se zyada 128 instruction "families" ho sakti hain.

KYUN saath, aur $2^7$ kyun? Har switch distinct patterns ki count double karta hai: 1 switch → 2 patterns, 2 switches → 4, aur generally $n$ switches → $2^n$. Yeh doubling is poore page ka akelaa counting rule hai, isliye ise abhi pakad lo:

PICTURE. Hum sirf un 7 orange switches ko zoom karte hain aur dekhte hain ki pattern count double hoti hai jab ek-ek karke switches light karte hain.

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Step 3 — Un 128 families mein se chaar legally tumhari hain

KYA HAI. 128 possible opcode patterns mein se, RISC-V spec permanently chaar ko non-standard (custom) use ke liye reserve karta hai. Unke bit patterns:

$$\text{custom-0}=\underset{\text{inst[6:0]}}{\underbrace{0001011}},\text{custom-1}=0101011,\text{custom-2}=1011011,\text{custom-3}=1111011$$

Un saath-digit strings mein se har ek Step 2 ke saath orange switches ki ek specific setting hai.

KYUN reserved? Spec ki taraf se ek promise: koi bhi future ratified standard extension kabhi yeh chaar patterns emit nahi karega. Toh agar tum koi instruction banao, maan lo opcode $0001011$ ke saath, woh kabhi kisi standard instruction se collide nahi karega — decoder kabhi confuse nahi hoga ki iska owner kaun hai. Yahi guarantee custom extensions ki poori legal foundation hai.

PICTURE. 128-slot opcode map, zyaadatar slots standard families ne claim ki hain, chaar slots tumhare liye glow kar rahe hain.

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Step 4 — Ek family ke andar: R-type shape udo

KYA HAI. Ek family (opcode) choose karna sirf 7 rightmost switches fix karta hai. Baaki 25 switches ($\text{inst[31:7]}$) abhi bhi free hain. Hum choose karte hain inhe standard R-type format ki tarah lay out karne ke liye — register-to-register template:

$$\underset{7\text{ bits}}{\underbrace{\text{funct7}}}\underset{5\text{ bits}}{\underbrace{\text{rs2}}}\underset{5\text{ bits}}{\underbrace{\text{rs1}}}\underset{3\text{ bits}}{\underbrace{\text{funct3}}}\underset{5\text{ bits}}{\underbrace{\text{rd}}}\underset{7\text{ bits}}{\underbrace{\text{opcode}}}$$

Accounting check karo: $7+5+5+3+5+7=32$. Har switch ke liye kuch kaha gaya hai.

KYUN R-type? Un fields mein se do data point karte hain aur teen operation identity point karte hain — aur yeh split agले step mein bahut important hai. Lekin immediate reason hardware reuse hai: register file mein pehle se do read ports aur ek write port hain. Ek R-type op do registers read karta hai ($\text{rs1},\text{rs2}$) aur ek likhta hai ($\text{rd}$), jo exactly wahi hai jo woh ports provide karte hain. Dekho R-type instruction format.

PICTURE. 32-switch row ko chhe R-type zones mein re-carve kiya, job ke hisaab se colour-coded.

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Step 5 — Key split: kaunse fields operation choose karte hain?

KYA HAI. Hum count karna chahte hain distinct operations per opcode slot — kitne genuinely alag instructions define kar sakte hain. Sirf woh fields count honge jo behaviour change karte hain. Toh hum $\text{funct3}$ aur $\text{funct7}$ rakhte hain, aur $\text{rs1},\text{rs2},\text{rd}$ ko ignore karte hain.

KYUN register fields ignore karein? Kyunki $\text{rs1}$ ko register 5 se register 6 change karna naya instruction nahi banata — woh same instruction ko alag data par run karta hai. mac x10,... aur mac x11,... same operation hai. Register combinations count karna data count karna hoga, operations nahi. Toh operation-selecting bits sirf yeh hain:

$$b_{\text{op}}=\underset{\text{funct3 bits}}{\underbrace{3}}+\underset{\text{funct7 bits}}{\underbrace{7}}=10\text{ bits}$$

PICTURE. Row ko "operation choose karta hai" half (funct3 + funct7, glowing) aur "data choose karta hai" half (teen register fields, dimmed) mein split kiya.

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Step 6 — Ek slot count karo: $2^{10}=1024$

KYA HAI. Step-2 ka counting rule 10 operation bits par apply karo:

$$N_{\text{ops per slot}}=2^{b_{\text{op}}}=2^{10}=\underset{\text{funct3}=8}{\underbrace{2^3}}\times \underset{\text{funct7}=128}{\underbrace{2^7}}=8\times 128=1024$$

8 possible $\text{funct3}$ patterns mein se har ek 128 possible $\text{funct7}$ patterns mein se kisi ke saath pair ho sakta hai, aur $8\times 128=1024$.

KYUN multiply karein? Kyunki dono fields independent hain — koi bhi $\text{funct3}$ value kisi bhi $\text{funct7}$ value ke saath kaam karti hai. Independent choices multiply hoti hain (same reason "3 shirts × 4 trousers = 12 outfits"). Agar independent na hote toh collisions subtract karne padte; yahan nahi karne padte.

PICTURE. Ek $8\times 128$ grid: rows = funct3 values, columns = funct7 values, har cell ek distinct instruction. Saari 1024 cells ek opcode slot ki hain.

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Step 7 — Chaar slots: $4\times 1024=4096$

KYA HAI. 4 reserved custom slots hain (Step 3), aur Step 6 ka grid unme se har ek ke andar baitha hai. Toh:

$$N_{\text{total}}=\underset{\text{custom-0..3}}{\underbrace{4}}\times \underset{\text{ops per slot}}{\underbrace{1024}}=4096$$

KYUN slots ko multiply karke add karein? Har slot ek fresh, non-overlapping opcode value hai, toh uske 1024 operations baaki slots ke operations se bilkul alag hain. Chaar identical, disjoint grids ek saath stack karein → $4\times 1024$.

PICTURE. Step-6 grid ki chaar copies, har ek custom opcode ke liye ek, total 4096.

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Step 8 — Edge & degenerate cases (taaki kabhi surprise na aaye)

KYA / KYUN / PICTURE, teen corners jo counting hide kar deti hai:

• All-zero function code ($\text{funct3}=000$, $\text{funct7}=0000000$). Yeh ek perfectly valid custom instruction hai, "no instruction" nahi — yeh grid ka ek specific cell hai (corner wala). Parent note mein MAC example exactly isi cell ka use karta hai. Kuch bhi degenerate nahi hota; zero ek legal code hai.
• Aisa core jo tumhara op implement nahi karta. 1024 cells available names hain, implemented units nahi. Agar silicon mein kisi cell ke peeche koi logic nahi hai, toh use execute karne par ek illegal-instruction trap uthega — ek clean, defined failure, kabhi silent wrong result nahi. (Isliye custom extensions kisi aur ke programs nahi todte; parent ka mistake box dekho.)
• Non-R-type shapes. Hamara 4096 sirf R-type-shaped ops count karta hai. Tum may un 25 upper bits ko alag tarike se carve kar sakte ho (jaise ek immediate field), function bits ko data bits ke liye trade karke — jo us slot ke liye operation count kam karta hai. Toh 4096 R-type maximum hai, har possible layout ki hard ceiling nahi.

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Ek-picture summary

Left se right padho: 32 switches → 7 opcode hain → 4 opcodes tumhare hain → har ek R-type mein carve hota hai → sirf 10 function bits operation pick karte hain → $2^{10}=1024$ per slot → $\times 4=4096$.

Recall Feynman: poora walkthrough plain words mein retell karo

Socho ek form 32 boxes wide hai jo har RISC-V command fill karta hai. Right side ke 7 boxes title box hain — woh batate hain kis type ka command hai, aur $2^7=128$ possible titles hain. RISC-V rule-makers ne un titles mein se chaar tumhare liye set aside kar diye hain taaki tum jo chaaho invent karo, promise karke ki woh unhe official commands ke liye kabhi use nahi karenge. Tumhare title ke andar, form mein abhi bhi 25 khali boxes hain. Agar tum unhe standard "R-type" tarike se fill karo, teen chote groups of boxes sirf batate hain ki kaunse storage slots read aur write karne hain (woh data hai, naya command nahi), jabki do groups — 3 boxes plus 7 boxes, kul das boxes — batate hain ki command aslaan kya karta hai. Das OFF/ON boxes $2^{10}=1024$ alag "kya-karta-hai" codes banate hain. Apne chaar titles se multiply karo aur tumhe $4\times 1024=4096$ commands milte hain jo tum design karne ke liye free ho. Aur agar kisi chip ne un codes mein se kisi ek ke peeche machine actually build nahi ki hai, toh use run karna bas politely refuse kar deta hai (traps) instead of kuch galat karne ke — isliye tumhari inventions kisi aur ke programs kabhi nahi todtiin.

Recall Quick self-test

$b$ switches kitne patterns banate hain? ::: $2^b$. Kaunse R-type fields operation choose karte hain (data nahi)? ::: funct3 (3 bits) aur funct7 (7 bits). Hum operations count karte waqt rs1/rs2/rd ko kyun ignore karte hain? ::: Woh data select karte hain (kaunse registers), nahi ki kaunsa operation run hoga. Ops per custom opcode slot? ::: $2^3\times 2^7=1024$. Total R-type custom ops chaaon slots mein? ::: $4\times 1024=4096$. Kya hota hai agar ek core ek unimplemented custom code execute kare? ::: Woh illegal-instruction trap raise karta hai — ek clean, defined failure.

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Connections

• RISC-V base ISA (RV32I / RV64I)
• R-type instruction format
• Instruction Set Architecture
• Rocket Chip and RoCC coprocessor interface
• Vector / SIMD extensions (RVV)
• Domain-specific architectures