6.5.11 · D1RISC-V custom extensions for accelerators
Ek processor sirf woh numbers samajhta hai jo secretly instructions hain — bits ka ek fixed-width pattern jisme kuch bits kehte hain kya karna hai aur kuch kehte hain kaunsa data use karna hai . RISC-V kuch bit-patterns ko permanently blank chhod deta hai taaki tum apna khud ka "yeh-karo" code invent kar sako jo ek custom hardware unit ko fire kare, bina kabhi normal software ko confuse kiye.
Custom instructions samajhne se pehle, tumhe ek plain instruction bit by bit padhna aana chahiye. Yeh page har woh word aur symbol build karta hai jis par parent note rely karta hai, "bit kya hota hai" se shuru hokar "kyun 1024 ops ek opcode slot mein fit hote hain" tak. Yahan kuch bhi assumed nahi hai — agar parent ne use kiya, to hum define karte hain.
Ek bit ek single yes/no switch hai: yeh ya to 0 1
Definition Bit pattern / wordEk word yahan exactly 32 0000000 00010 00001 000 00011 0110011 hai hi aisa ek 32-bit word — koi alag "instruction cheez" nahi hoti, bas ek number jise CPU command ki tarah interpret karne par agree karta hai.
Figure dekho: 32 chhote boxes ek row mein, right se numbered. Sabse rightmost box bit 0 31 right waale boxes pehle padhkar.
inst[6:0]
Square-bracket slice inst[6:0] ka matlab hai: "inst naam ke word ko lo aur sirf bits 6 , 5 , 4 , 3 , 2 , 1 , 0 sabse rightmost 7 boxes . High-number pehle, low-number baad mein likha jaata hai. To inst[6:0] ek 7-bit sub-pattern hai.
Topic ko iske ki zaroorat kyun hai: woh 7 bits opcode hain — sabse pehli cheez jo hardware padh kar jaanta hai ki instruction kaunsi family ki hai. "Custom opcode space" ka poora idea inst[6:0] ke possible values ke baare mein ek statement hai.
Opcode inst[6:0] mein pattern hai. Yeh ek sawaal ka jawaab deta hai: yeh word kaisi category ki operation hai? — ek add? ek load? ek branch? koi custom cheez?
Kyunki 7 bits 2 7 = 128 128
Intuition 7 bits kyun, aur kyun yeh poore topic ka anchor haiHar RISC-V instruction, chahe kisi bhi shape ki ho, apne opcode ke roop mein same rightmost 7 bits use karti hai. Yeh contract hai: normal software sirf kuch specific opcode values emit karta hai, to agar RISC-V kabhi nahi use karne ka promise kare standard instructions ke liye chaar specific patterns ko, toh woh chaar hamesha ke liye tumhare hain. Yeh promise literally chaar numbers ke baare mein ek promise hai jo tum inst[6:0] mein rakh sakte ho.
Ek register ek tiny, ultra-fast storage box hai CPU ke andar jo ek word hold karta hai. RISC-V mein 32 hote hain, x 0 x 31
32 registers mein se ek ka naam lene ke liye tumhe 0 31 2 5 = 32 5 bits exactly ek register naam karte hain.
rs1, rs2, rd
Yeh ek instruction ke andar 5-bit fields hain:
rs1 = "r egister s ource 1 " — pehla input.rs2 = "r egister s ource 2 " — doosra input.rd = "r egister d estination" — jahan answer jaata hai.
Yeh kaunsa data choose karte hain, kaunsi operation nahi. Yeh distinction yaad rakho — yeh poore "encoding budget" calculation ka seed hai.
Figure register file ko 32 boxes ki stack ke roop mein dikhata hai jisme se do arrows nikalte hain (do read ports , rs1 aur rs2 ko feed karte hue) aur ek arrow andar jaata hai (ek write port , rd se driven). Yahi exact shape — two read, one write — kyun parent note baar baar kehta hai "hardware barely changes": tumhari custom instruction sirf unhi ports mein plug hoti hai jo already exist karti hain.
Jab opcode keh deta hai "yeh ek arithmetic-shaped instruction hai", CPU ko phir bhi jaanna hota hai kaunsi wali: add? subtract? multiply? Yeh extra selector bits funct fields hain.
funct3 aur funct7
funct3 = ek 3-bit sub-selector.funct7 = ek 7-bit sub-selector.
Mil ke yeh opcode ko refine karte hain: opcode room choose karta hai, funct3/funct7 us room ke andar exact operation choose karte hain. Yeh operation select karte hain, kabhi data nahi.
Intuition Selector ko do pieces (3 + 7) mein kyun split kiya?Historically 3-bit funct3 ek handy spot par baithta hai aur common cases ko cheaply cover karta hai; wider funct7 rare variants ke liye extra room deta hai (jaise add ko subtract se distinguish karna jo otherwise identical lagte hain). Hamare purposes ke liye split matter nahi karta — jo matter karta hai woh hai total free selector bits, jinhe hum aage add karenge.
Definition R-type instruction formatR-type ("register type") woh instruction shape hai jo do registers padhti hai aur ek likhti hai. Iske 32 bits aise carved up hain:
7 funct7 5 rs2 5 rs1 3 funct3 5 rd 7 opcode 7 + 5 + 5 + 3 + 5 + 7 = 32
Figure har field ko colour karta hai: do data fields (rs2, rs1, rd) ek hue mein, do operation-selector fields (funct7, funct3) doosre mein, aur opcode teesre mein. Custom instructions is exact skeleton ko borrow karti hain taaki CPU ki existing decode wiring reuse ho sake — dekho R-type instruction format .
Common mistake "Register fields help choose karti hain ki kaunsi operation run hogi."Kyun sahi lagta hai: woh right there instruction mein hain, to surely contribute karti hain.
Fix: rs1/rs2/rd sirf yeh pick karte hain ki inputs aur output kaunse boxes mein hain. mac x1,x2,x3 aur mac x4,x5,x6 same operation hai alag data par. Sirf opcode + funct3 + funct7 decide karte hain operation kya hai .
Ab parent ki key derivation mein har symbol defined hai, to hum actually count kar sakte hain.
Intuition Counting principle (kyun hum powers of two use karte hain)Agar ek field k 2 k combinations count karne ke liye tum unke counts multiply karte ho.
Worked example Haath se sanity check2 3 = 8 2 7 = 128 8 × 128 = 1024 1024 × 4 = 4096
Definition Clock cycle & latencyEk clock cycle CPU ki sabse chhoti heartbeat of time hai. Latency = kitne cycles tum result maangne aur paane ke beech wait karte ho. Kam cycles = faster.
Definition Memory-mapped I/O (MMIO)MMIO ek tarika hai CPU ke bahar hardware se baat karne ka, special memory addresses padhke/likhke. Yeh kaam karta hai, lekin har round-trip ek slow bus cross karta hai — hundreds of cycles . Dekho Memory-mapped I/O .
Intuition Kyun ek custom instruction small, frequent ops ke liye jeetti haiEk custom instruction pipeline ke andar rehti hai: inputs seedha registers se aate hain (near-zero cost), result seedha wapis register mein jaata hai — few cycles . MMIO sirf operands deliver karne mein hundreds of cycles kharch kar deta. Yeh "unit kitni paas hai?" waala sawaal exactly woh tightly-coupled vs loosely-coupled choice hai jo parent describe karta hai — aur yahi reason hai custom instructions exist karti hain. Compare karo Hardware accelerators vs general-purpose CPUs se.
Speedup = (pehle ka time) ÷ (baad ka time). 5 ×
Intuition Kyun Amdahl's Law har accelerator ko limit karta haiAgar tum sirf us part ko speed up karo jo program ka, maano, 80% time leta tha, baki 20% phir bhi purani speed par chalta hai — to total gain cap ho jaata hai chahe accelerator kitna bhi fast ho. Isliye parent insist karta hai pehle profile karo aur sirf hot kernel ko harden karo. Poora treatment Amdahl's Law mein.
Upar se neeche padho: bits ek word banate hain; word ke rightmost 7 bits opcode hain; opcode plus funct fields plus register fields R-type row banate hain; funct bits count karne se 1024 budget milta hai; reserved opcodes plus woh budget ek custom extension dete hain, aur latency/coupling aur speedup ideas batate hain kab build karna worth it hai .
Ek RISC-V opcode kitne bits ka hota hai, aur kahan baithta hai? 7 bits, inst[6:0] mein — 32-bit word ke rightmost 7 boxes.
5 bits ek register kyun naam karte hain? Kyunki 32 registers hain aur 2 5 = 32
rs1, rs2, rd kya select karte hain — operation ya data?Data (kaunse registers inputs/output hold karte hain), kabhi operation nahi.
funct3 aur funct7 kya select karte hain?Ek opcode family ke andar specific operation (flavour).
Ek R-type instruction mein field by field kitne bits total hote hain? 7 + 5 + 5 + 3 + 5 + 7 = 32
Ek k 2 k Har added bit possibilities ko double kar deta hai.
Operations per custom slot derive karo. 2 3 × 2 7 = 8 × 128 = 1024
Ek custom instruction small ops ke liye MMIO se faster kyun hai? Operands few cycles mein registers se aate hain, na ki hundreds-of-cycles bus round-trip mein.
Amdahl's Law accelerators ke baare mein kya warn karta hai? Un-accelerated part total speedup cap kar deta hai, isliye sirf hot kernel ko harden karo.