6.4.2 · D3 · Hardware › Power, Thermal & Reliability › Dynamic voltage and frequency scaling (DVFS)
Intuition Yeh page kya hai
Dynamic voltage and frequency scaling (DVFS) parent note ne tumhe laws diye. Yahan hum unhe use karte hain jab tak kuch bhi surprise nahi kar sakta. Hum har tarah ke DVFS questions se gujarte hain — proportional scaling, voltage-only scaling, leakage floor, deadline limits, woh break-even jahan slow karna help karna band kar deta hai, aur ek degenerate "zero headroom" case. Har example batata hai ki woh matrix ka kaunsa cell fill karta hai.
Koi bhi symbol aane se pehle, yeh chhota sa dictionary hai jo hum baar baar use karenge. Neeche kuch bhi is line se pehle use nahi hota.
Definition Char quantities aur unki pictures
V = supply voltage = kitni force se hum electrons ko gates mein push karte hain. Picture: ek water pressure dial.
f = clock frequency = har second mein kitni baar har gate ko switch karne ka signal milta hai. Picture: ek metronome tick karta hua.
P = power = energy jo har second burn hoti hai (watts). Picture: ek aag ki unchai .
E = energy = power multiply karo kitne time tak chale (joules). Picture: kul jalaya gaya fuel = aag ki unchai × time.
Woh ek law jo sab kuch drive karta hai: dynamic power P = C eff V 2 f . Voltage squared enter karta hai (pressure dial badlao toh aag tezi se badhti hai), frequency linearly enter karti hai.
Har DVFS numeric question in cells mein se kisi ek mein fit hota hai. Jo example har cell ko fill karta hai, woh last column mein likha hai.
Cell
Case class
Isme kya khaas hai
Filled by
A
Proportional scaling V , f dono factor k se girte hain
Clean k 2 energy rule
Ex 1
B
Frequency-only scaling
Voltage fixed rehti hai → sirf linear savings
Ex 2
C
Voltage + frequency saath, unequal factors
Realistic "bada faayda" wala case
Ex 3
D
Fixed-work batch task (race-to-idle question)
Slower jeet sakta hai — total energy compare karo
Ex 4
E
Static-leakage floor
Limiting case: bahut dheere chalo → leakage dominate karta hai
Ex 5
F
Degenerate / zero headroom (hard deadline)
DVFS forbidden — f m i n > jo available hai
Ex 6
G
Break-even point (limiting value)
Woh k dhoondo jahan dono strategies tie karein
Ex 7
H
Real-world word problem (battery life)
Physics ko ek phone-user story mein wrap karo
Ex 8
Hum ek hi P-state table use karte hain poore mein (parent note se match karta hua):
P-State
V
f
dynamic P
P0
1.35 V
4.0 GHz
95 W
P1
1.20 V
3.5 GHz
65 W
P2
1.05 V
2.8 GHz
40 W
P3
0.90 V
2.0 GHz
22 W
Worked example Example 1 — dono
V aur f ko 20% girao
Ek task ko fixed number of clock cycles N chahiye. Hum abhi ( V 1 , f 1 ) par chal rahe hain. Hum ( V 2 , f 2 ) par scale karte hain jahan V 2 = 0.8 V 1 aur f 2 = 0.8 f 1 (toh k = 0.8 ). Task ke liye energy kis fraction se giregi, aur time kitna zyada lagega?
Forecast: abhi andaaza lagao — kya saving 20%, 36%, ya 64% hai? Likh lo.
Fixed-work task ke liye energy likho. Time = N / f (cycles ÷ cycles-per-second). Energy = P ⋅ t = ( C V 2 f ) ⋅ ( N / f ) = C V 2 N .
Yeh step kyun? Power ke andar ka f aur time ke denominator ka f cancel ho jaate hain. Toh energy-per-task sirf V 2 par depend karta hai — yahi poori trick hai.
Dono operating points ka ratio nikalo. E 1 E 2 = C V 1 2 N C V 2 2 N = ( V 1 V 2 ) 2 = k 2 = 0. 8 2 = 0.64.
Yeh step kyun? C aur N same task ke hain, toh divide ho jaate hain — sirf voltage ratio bachta hai, squared.
Energy saving = 1 − 0.64 = 0.36 = 36% .
Time cost. t 2 / t 1 = f 1 / f 2 = 1/0.8 = 1.25 , matlab 25% zyada time .
Yeh step kyun? Same cycles 0.8× tick rate par ⇒ 1.25× wall-clock time lagega.
Verify: units — C [ F ] ⋅ V 2 [ V 2 ] ⋅ N [ count ] ke dimensions energy jaise hain ek constant tak, aur dono points mein same hai, toh ratio unitless hai. Sanity: voltage squared gaya, toh 20% cut se 20% se zyada saving honi chahiye — 36% > 20%. ✓
Worked example Example 2 —
f ko half karo, V fixed rakho
Humein voltage V par rakhna padega (shayad regulator locked hai), lekin frequency half kar lete hain: f ′ = 0.5 f . Power ka kya hoga, aur fixed-work task ke liye energy ka?
Forecast: kya energy giregi, same rahegi, ya badhegi?
Power. P ′ = C V 2 ( 0.5 f ) = 0.5 P . Power half ho jaati hai — f mein linear .
Yeh step kyun? V nahi badla, toh V 2 factor frozen hai; sirf f multiplier hilt hai.
Fixed work ke liye energy. E = C V 2 N mein koi f nahi hai . Toh E ′ = E — energy unchanged rehti hai!
Yeh step kyun? Hum half power par chal rahe hain lekin double time ke liye. Aadhi aag double time ke liye = same fuel.
Verify: E ′ / E = ( 0.5 P ) ⋅ ( 2 t ) / ( P ⋅ t ) = 1 . ✓ Yahi wajah hai ki parent note "sirf frequency reduce karna" ko galti kehta hai — tum instantaneous power bachate ho lekin energy nahi jo battery ko matter karti hai, jab tak voltage bhi na gire.
Worked example Example 3 — real P-state jump P0 → P2
P0 ( 1.35 V , 4.0 GHz ) se P2 ( 1.05 V , 2.8 GHz ) par jao. Tabulated power check karo, phir fixed-work energy saving nikalo.
Forecast: P0 ki power ka roughly kaunsa fraction P2 hai — aadha? teesra?
Law se P2 power predict karo. P 0 P 2 = ( V 1 V 2 ) 2 f 1 f 2 = ( 1.35 1.05 ) 2 ⋅ 4.0 2.8 .
Yeh step kyun? Dono factors change hote hain, toh squared-voltage ratio ko linear-frequency ratio se multiply karte hain.
Compute karo. ( 0.7778 ) 2 = 0.6049 ; times 0.70 = 0.4234 . Toh predicted P 2 ≈ 0.4234 × 95 = 40.2 W .
Yeh step kyun? Table 40 W list karta hai — hamara derived law datasheet reproduce karta hai, confirm karta hai ki C eff roughly states ke across constant hai.
Fixed-work energy ratio. Sirf V 2 matter karta hai: E 2 / E 0 = ( 1.05/1.35 ) 2 = 0.6049 , yaani 39.5% energy saving , 4.0/2.8 = 1.43 × zyada time ki cost par.
Verify: 40.2 W ≈ 40 W table value (0.5% ke andar). Ratios ke units unitless hain. ✓
Worked example Example 4 — ek video encode karo: fast vs slow
Ek 1-ghante ke encode ko N = 1 0 12 cycles chahiye. Option A = P0 par chalo, aur Option B = P2 par chalo compare karo. Abhi leakage ignore karo (Ex 5 mein add hoga).
Forecast: kaun zyada total energy use karega — fast wala ya slow wala?
Option A time & energy. t A = 1 0 12 / ( 4.0 × 1 0 9 ) = 250 s ; E A = 95 × 250 = 23 , 750 J .
Yeh step kyun? cycles ÷ (cycles/s) = seconds; phir energy = power × seconds.
Option B time & energy. t B = 1 0 12 / ( 2.8 × 1 0 9 ) = 357.1 s ; E B = 40 × 357.1 = 14 , 286 J .
Compare karo. Saving = ( 23750 − 14286 ) /23750 = 39.8% energy, 43% zyada time ke liye.
Yeh step kyun? Yeh Race-to-idle vs race-to-dark question hai: koi leakage floor nahi hone par, flexible-deadline batch work ke liye slower jeet jaata hai.
Verify: E A = C V P 0 2 N aur E B = C V P 2 2 N ⇒ ratio Ex 3 ke 0.6049 ke barabar hona chahiye; indeed 14286/23750 = 0.6015 (tabulated 40 W ki rounding mein match karta hai). ✓
Worked example Example 5 — jab dheere chalna faaydemand karna band kar deta hai
Real total power hai P total = dynamic C V 2 f + static V I leak . Video encode dobara karo leakage current I leak = 8 A add karke (jab tak powered hai tab tak fixed).
Forecast: kya leakage add karne se slow option kam attractive ho jaata hai?
Har state par leakage power. P0: 1.35 × 8 = 10.8 W . P2: 1.05 × 8 = 8.4 W .
Yeh step kyun? Static power V ⋅ I leak hai — yeh sirf isliye nahi khatam hoti ki switching slow hai; yeh tab tak flow karta hai jab tak chip on hai.
Total power. P0: 95 + 10.8 = 105.8 W . P2: 40 + 8.4 = 48.4 W .
Total energy. A: 105.8 × 250 = 26 , 450 J . B: 48.4 × 357.1 = 17 , 286 J .
Yeh step kyun? Slow B 43% zyada time chalta hai, toh leakage zyada time ke liye pay karta hai . Yeh fayde ko thoda kam karta hai.
Nayi saving = ( 26450 − 17286 ) /26450 = 34.6% — 39.8% se kam.
Yeh step kyun? Leakage hamesha jaldi khatam karne ko favour karta hai. Jaise leakage badhta hai, break-even race-to-idle ki taraf shift hota hai. Deep-submicron nodes mein jahan leakage power ka 20–40% hoti hai, yeh answer poora palat sakta hai — Power gating ko motivate karta hai.
Verify: leakage-only energy: A pays 10.8 × 250 = 2700 J , B pays 8.4 × 357.1 = 3000 J — B zyada leakage pay karta hai, exactly yahi wajah hai ki uska advantage kam hua. Inhe Ex 4 ki dynamic energies mein add karne se step 3 reproduce hota hai (23750 + 2700 = 26450 ; 14286 + 3000 = 17286 ). ✓
Worked example Example 6 — ek deadline jise DVFS honour nahi kar sakta
Ek robot control loop ko 5 × 1 0 6 cycles 1 ms deadline ke andar khatam karni hai. Maximum available frequency 4.0 GHz hai. Kya hum power bachane ke liye DVFS use kar sakte hain?
Forecast: haan, nahi, ya "sirf optimisation ke baad"?
Required frequency. f m i n = 1 × 1 0 − 3 s 5 × 1 0 6 cycles = 5 × 1 0 9 Hz = 5 GHz .
Yeh step kyun? Tumhe deadline se pehle saare cycles push karne hain: cycles ÷ time = minimum tick rate.
Available se compare karo. 5 GHz > 4.0 GHz ⇒ P0 bhi (sabse tez ) bahut slow hai. Headroom negative hai.
Yeh step kyun? DVFS sirf f ko max se neeche laata hai. Agar deadline already max se zyada demand karti hai, toh scale down karne ke liye kuch nahi hai — yeh degenerate cell hai.
Resolution. Kaam kam karo: code ko 4 × 1 0 6 cycles tak optimise karo. Phir f m i n = 4 × 1 0 9 = 4.0 GHz , exactly P0, 20% cycle margin ke saath.
Yeh step kyun? Jab speed nahi badha sakte, toh kaam hatana padta hai — Real-time systems scheduler phir CPU ko P0 par pin karta hai bina kisi DVFS freedom ke.
Verify: 4 × 1 0 6 / ( 4.0 × 1 0 9 ) = 1.0 × 1 0 − 3 s = 1 ms exactly — deadline just meet hui. ✓
Worked example Example 7 — kis
k par slow karna energy bachana band kar deta hai?
k se proportional scaling dynamic energy deti hai ∝ k 2 (Ex 1) lekin runtime ∝ 1/ k , toh leakage energy ∝ 1/ k . Total per-task energy (units mein jahan dynamic-at-k = 1 = 1 aur leakage-at-k = 1 = L ):
E ( k ) = k 2 + k L .
Woh k nikalo jo minimise kare total energy jab leakage ratio L = 0.3 ho.
Forecast: kya best k 1 ke kareeb hai (tez chalo) ya 0 ke kareeb (rengno)?
Minimum kyun exist karta hai. Jaise k → 0 , dynamic k 2 → 0 lekin leakage L / k → ∞ (forever rengna = forever leak karna). Jaise k → 1 , leakage sasta hai lekin dynamic maximum hai. Toh kahin beech mein, E ( k ) bottom out karta hai — ek classic limiting-behaviour tug-of-war.
Derivative kyun yahan? Ek smooth valley ka bottom wahan hota hai jahan slope zero ho — derivative exactly jawab deta hai "kahan slow jaana help karna band kar deta hai?"
Slope zero set karo. d k d E = 2 k − k 2 L = 0 ⇒ 2 k 3 = L ⇒ k = ( 2 L ) 1/3 .
L = 0.3 plug in karo. k = ( 0.15 ) 1/3 = 0.5313.
Yeh step kyun? Is k se neeche, zyada lambe runtime se aane wali extra leakage shrinking dynamic energy se zyada ho jaati hai — "race-to-dark" boundary.
Verify: second derivative E ′′ ( k ) = 2 + 2 L / k 3 > 0 , minimum confirm karta hai. Numeric check: E ( 0.53 ) = 0.281 + 0.566 = 0.847 vs E ( 0.45 ) = 0.203 + 0.667 = 0.870 (worse) aur E ( 0.65 ) = 0.423 + 0.462 = 0.884 (worse) — 0.53 sach mein valley hai. ✓
Worked example Example 8 — phone kitna zyada chalega?
Ek phone ka CPU average 15% utilisation par chalta hai jab user padhta hai. No DVFS (hamesha P0, 95 W) ko DVFS se compare karo jo har 10 s mein 8 s P3 (22 W) par aur 2 s P0 (95 W) par spend karta hai. Agar same battery sab kuch drive karti hai, toh browsing session kitne factor se lamba hoga? (Assume CPU draw dominate karta hai.)
Forecast: 1.5×, 2×, ya 2.5× zyada lambi?
DVFS ke bina average power. Fixed P0 ⇒ P ˉ fixed = 95 W .
DVFS ke saath average power. P ˉ dvfs = 10 22 × 8 + 95 × 2 = 10 176 + 190 = 36.6 W .
Yeh step kyun? Average power = ek representative 10 s window mein total energy ÷ 10 s. Quadratic V 2 idle stretches ko bahut sasta banata hai.
Battery life factor. Same fixed energy budget E batt : life = E batt / P ˉ , toh ratio = P ˉ fixed / P ˉ dvfs = 95/36.6 = 2.60.
Yeh step kyun? Life average draw ke inversely proportional hai; dono averages divide karne se multiplier milta hai.
Verify: energy saved fraction = 1 − 36.6/95 = 61.5% — parent note ke web-browsing example se match karta hai. Life factor = 1/ ( 1 − 0.615 ) = 2.60 . ✓ Yeh "2–3× battery" claim concrete ban jaata hai; CPU scheduling governor wahi hai jo in P-states ko Processor performance counters se pick karta hai.
Recall Quick self-test
Sirf frequency half karne se fixed-work energy kaise change hoti hai? ::: Bilkul nahi — energy = C V 2 N mein koi f nahi; tum half power par double time ke liye chalte ho.
k = 0.8 se proportional scaling energy ka kaunsa fraction bachati hai? ::: 1 − k 2 = 36% .
Leakage race-to-idle ko kyun favour karta hai? ::: Static power V I leak har second pay hota hai jab chip on hoti hai; dheere chalna matlab usse zyada time tak pay karna.
DVFS kab impossible hai? ::: Jab deadline f m i n demand kare jo maximum available frequency se upar ho (negative headroom).
Leakage ratio L ke saath, energy-optimal proportional factor kya hai? ::: k = ( L /2 ) 1/3 .
"Volts squared, freq bare, leakage everywhere." — voltage quadratically bachata hai, frequency sirf linearly, aur leakage tab tak jalta rehta hai jab tak tum jaage ho.