Visual walkthrough — Dynamic voltage and frequency scaling (DVFS)

6.4.2 · D2 · Hardware › Power, Thermal & Reliability › Dynamic voltage and frequency scaling (DVFS)

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Step 1 — "Gate switching" actually hota kya hai

KYA HAI. Chip ke andar sabse chhota event ek single logic gate ka off se on flip karna hai. Physically, flipping ka matlab hai electric charge ka ek chhota bucket bharna ya khaali karna. Us bucket ko capacitor kehte hain, aur woh per volt kitna charge hold karta hai woh uski capacitance $C$ hai.

YAHAN SE KYUN SHURU KAREIN. Baaki sab kuch — power, heat, battery life — bas yahi ek event hai jo ek second mein billions of times repeat hota hai. Agar hum ek flip ki cost samajh lein, toh hum chip samajh lenge.

PICTURE. Neeche, switch (ek MOSFET transistor) supply rail ko voltage $V$ par capacitor $C$ se connect karta hai. Jab switch close hota hai, charge tab tak flow karta hai jab tak capacitor voltage $V$ tak nahi pahunch jaata.

The relation $Q=CV$ bas yeh kehti hai: bada bucket ($C$) ya zyada pressure ($V$) → zyada charge stored.

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Step 2 — Ek flip ki energy cost

KYA HAI. Hum woh energy compute karte hain jo supply bucket ko empty se voltage $V$ tak bharne mein spend karti hai.

INTEGRAL KYUN, AUR SIRF "CHARGE TIMES VOLTAGE" KYUN NAHI? Yeh woh subtle point hai jo zyaatar log miss karte hain. Agar tum naively kehte "energy $=Q\times V=C{V}^2$", toh tum galat hote, kyunki bucket ke across voltage $V$ poore time nahi hoti — jaise charge trickle karta hai waise woh $0$ se $V$ tak climb karti hai. Humein charge ke har chhote tukde $dQ$ pe $V\cdot dQ$ add karna hoga, aur har tukda us voltage par enter karta hai jo bucket us waqt hold kar rahi hoti hai. Woh "bahut saare chhote pieces add karna" exactly wahi hai jo ek integral karta hai — isliye yahan integral tool aata hai aur koi simpler cheez kaam nahi karegi.

$$E_{\text{switch}}=\underset{\text{sum over all charge levels}}{\underbrace{{\int }_0^V}}\underset{\text{voltage right now}}{\underbrace{v}}\underset{\text{tiny charge }dQ=Cdv}{\underbrace{Cdv}}=\frac{1}{2}C{V}^2$$

• ${\int }_0^V$ — "bucket voltage ko $0$ se final $V$ tak sweep karo."
• $v$ — instantaneous voltage (lower-case), jaise hum fill karte hain waise change hoti hai.
• $Cdv$ — charge ka woh sliver jo tab add hota hai jab voltage $dv$ se badhti hai (kyunki $Q=Cv\Rightarrow dQ=Cdv$).

PICTURE. Energy $v$–$Q$ line ke neeche ka area hai. Kyunki voltage charge ke saath linearly badhti hai, woh area ek triangle hai — aur ek triangle rectangle $C{V}^2$ ka aadha hota hai. Yahan se factor $\frac{1}{2}$ paida hota hai.

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Step 3 — Ek flip se power tak (flips per second)

KYA HAI. Chip ek baar flip nahi karti; woh har clock tick pe flip karti hai. Clock frequency $f$ yeh hai ki ek second mein kitne ticks hote hain (dekhein Clock generation and PLs ki woh clock kaise banayi jaati hai). Har gate har tick pe flip nahi karta, isliye hum ==activity factor $\alpha$== introduce karte hain — woh fraction jo batata hai ki average tick pe kitne gates actually switch karte hain.

KYUN. Power ka matlab hai energy per second. Isliye hum ek flip ki cost ko flips per second se multiply karte hain.

$$P_{\text{dynamic}}=\underset{\text{energy per flip}}{\underbrace{\frac{1}{2}C{V}^2}}\times \underset{\text{flips per second}}{\underbrace{\alpha f}}=\underset{\frac{1}{2}\alpha C}{\underbrace{C_{\text{eff}}}}{V}^{2}f$$

• $\alpha$ — activity factor, $0$ (kuch switch nahi kar raha) aur $1$ (sab kuch switch kar raha hai) ke beech.
• $f$ — clock ticks per second.
• $C_{\text{eff}}=\frac{1}{2}\alpha C$ — constants ka ek bundle, "effective capacitance."

PICTURE. Ek bucket brigade socho: har flip energy ka ek bucket khaali karta hai, aur $f$ set karta hai ki line kitni fast move karti hai. Faster clock = zyada buckets per second = zyada power.

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Step 4 — Tum sirf voltage kyun nahi drop kar sakte (constraint)

KYA HAI. Tum soch sakte ho: "$V^2$ itna powerful hai — bas voltage ko almost zero tak crash karo aur $f$ ko high rakho!" Physics kehti hai nahi. Voltage kam karne se har flip slower hoti hai, aur agar ek flip agla clock tick aane se pehle finish nahi hui, toh chip garbage compute karta hai.

DELAY KO VOLTAGE SE KYUN BANDHA JAATA HAI? Switch ki drive current — woh kitni fast bucket mein charge shovels kar sakti hai — depend karti hai ki supply voltage transistor ke ==threshold voltage $V_{th}$== (woh voltage jiske neeche transistor barely conduct karta hai) se kitna upar hai. Bucket fill karne mein delay hai:

$$t_{\text{delay}}\propto \frac{C{V}_{dd}}{I_{\text{drive}}},I_{\text{drive}}\propto (V_{dd}-V_{th}{)}^2\Rightarrow t_{\text{delay}}\propto \frac{V_{dd}}{(V_{dd}-V_{th}{)}^2}$$

• $V_{dd}$ — supply voltage (upar wala $V$ hi hai; $dd$ bas "drain supply rail" mark karta hai).
• $V_{th}$ — threshold voltage, transistor ki ek fixed property.
• $(V_{dd}-V_{th})$ — woh "headroom" jo actually current drive karta hai. Jaise $V_{dd}$, $V_{th}$ ke paas aata hai, yeh shrink hota hai, current collapse hoti hai, aur delay explode kar jaati hai.

Kyunki clock period delay se zyada honi chahiye ($1/f\ge t_{\text{delay}}$), ek slower switch lower maximum frequency force karta hai:

$$\boxed{f_{\max }\propto (V_{dd}-V_{th}{)}^{\gamma }},\gamma \approx 1.5\text{–}2$$

PICTURE. Jaise $V_{dd}$ neeche $V_{th}$ ki taraf slide karta hai, max frequency curve zero ki taraf bend hoti hai — ek wall jise tum cross nahi kar sakte. Voltage regulators $V_{dd}$ set karte hain; clock ko is wall ko respect karna hoga.

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Step 5 — Proportional scaling: $k^2$ energy result

KYA HAI. Ab hum unhe same factor $k$ se chain karte hain aur dekhte hain ki poore task ki energy ka kya hota hai. Maano ek task ko fixed number of clock cycles $N$ chahiye (fixed kyunki kaam fixed hai, chahe tum kitna bhi fast clock karo).

TASK PER ENERGY KYUN COUNT KAREIN, POWER NAHI? Power akele misleading hai — slower chalana matlab longer chalna. Energy (power × time) battery drain ka honest measure hai. Dekho frequency kaise cancel hoti hai:

$$\text{Time}=\frac{N}{f},\text{Energy}=P\cdot \text{Time}=\left(C_{\text{eff}}{V}^{2}f\right)\cdot \frac{N}{f}=C_{\text{eff}}{V}^{2}N$$

• Power mein $f$ aur time mein $f$ cancel ho jaate hain. Astonishing: task energy frequency pe bilkul depend nahi karti — sirf $V^2$ pe!

Ab dono ko down scale karo: $V_2=k{V}_1$ aur $f_2=k{f}_1$ (jahan $0<k\le 1$):

$$\frac{E_2}{E_1}=\frac{C_{\text{eff}}(k{V}_1{)}^{2}N}{C_{\text{eff}}{V}_1^{2}N}=\boxed{k^2}$$

PICTURE. Neeche, task per energy scaling factor ke square ki tarah girती hai jabki time sirf linearly badhta hai ($\propto 1/k$). $k=0.8$ par: energy $=0.64$ ($36\%$ bachao), time $=1.25\times$ ($25\%$ zyada).

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Step 6 — Edge case: static leakage fairy tale tod deti hai

KYA HAI. Upar sab kuch dynamic power tha (flipping se). Lekin jab ek gate kuch nahi karta tab bhi, transistors powered on rehne ki wajah se current ka ek trickle leak karte hain. Yeh static leakage power hai:

$$P_{\text{total}}=\underset{\text{dynamic (falls with }{k}^2)}{\underbrace{C_{\text{eff}}{V}^{2}f}}+\underset{\text{static leakage}}{\underbrace{V\cdot I_{\text{leak}}}}$$

YEH KYUN MATTER KARTA HAI — DEGENERATE LIMIT. $k$ ko bahut chhota push karo (bahut slowly chalo): dynamic power $k^2$ ki tarah vanish hoti hai, lekin task ab bahut lamba time leta hai ($\propto 1/k$), aur leakage poore time energy bleed karta rehta hai. Kuch sweet-spot frequency ke neeche, slower jana actually zyada total energy cost karta hai. Yahi poora Race-to-idle vs race-to-dark debate hai: kabhi kabhi "fast chalo, phir so jao" (aur leakage cut karne ke liye Power gating use karo) crawling se better hota hai.

PICTURE. Total-energy-vs-frequency curve ek valley hai: bahut slow crawl karo aur leakage dominate karta hai (left wall utha), bahut fast sprint karo aur $V^2$ dominate karta hai (right wall utha). Bottom true optimum hai.

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Ek-picture summary

Is page ki sari cheezein, compress karke: ek flip costa hai $\frac{1}{2}C{V}^2$ (area ka triangle) → billions of flips per second deta hai $P=C_{\text{eff}}{V}^{2}f$ → voltage aur frequency $f_{\max }$ wall se chain hain → dono ko $k$ se scale karna task energy ko $k^2$ se shrink karta hai → jab tak leakage curve ko wapas valley mein bend nahi kar deti.

Recall Feynman retelling — plain words mein wapas bolo

Chip ke andar, kuch bhi karna matlab hai chhote chhote electric charge ke buckets ko bharna aur khaali karna. Ek bucket bharne ki cost energy ke barabar hoti hai jo half capacitance times voltage squared hai — squared part is liye aata hai kyunki bucket voltage gradually badhti hai filling ke dauran, isliye energy ek triangle hai, rectangle ka aadha.

Chip har clock tick pe buckets fill karti hai, isliye power ek fill ki cost times ticks per second hai: power straight-line badhti hai clock ke saath lekin squared badhti hai voltage ke saath. Yahi lopsidedness poora point hai.

Tum sirf voltage crush karna chahoge squaring ki wajah se — lekin lower voltage se har bucket fill slowly hoti hai, aur agar ek bucket agla tick aane se pehle full nahi hua, toh answer garbage hai. Isliye voltage aur clock handcuffed hain: ek lower karo, doosra bhi lower karna padega.

Jab tum ek task chalane ke liye dono ko same fraction $k$ se lower karte ho, clock cancel ho jaata hai (slower matlab longer, aur dono effects trade off karte hain), energy $\propto V^2\propto k^2$ reh jaati hai. Sab kuch 80% tak drop karo aur tum sirf 64% energy rakhte ho — 25% longer wait ke liye 36% saving.

Catch yeh hai: transistors wahan baithe baithe power leak karte hain. Bahut slowly crawl karo aur tum itna lamba leak karte ho ki tum haar jaate ho. Isliye sabse smart move hai valley dhundhna — sabse slow speed nahi, balki sweet spot — ya fast chalo aur phir poora block off kar do.

Recall

Dynamic-only model mein task per energy frequency se independent kyun hai? ::: Power $\propto f$ hai, lekin time $\propto 1/f$ hai, aur energy = power × time, isliye $f$ cancel ho jaata hai — energy $\propto V^2$ reh jaati hai. Voltage aur frequency saath scale kyun hone chahiye? ::: Lower voltage har transistor switch ko slow kar deti hai ($t_{\text{delay}}$ badhta hai), isliye $f_{\max }\propto (V_{dd}-V_{th}{)}^{\gamma }$ girta hai — tum low voltage par high clock nahi rakh sakte warna logic time pe finish nahi hogi. $\frac{1}{2}C{V}^2$ mein $\frac{1}{2}$ factor kahan se aata hai? ::: Bucket voltage fill hote waqt 0 se V tak climb karti hai, isliye energy $v$–$Q$ line ke neeche triangular area hai, jo full rectangle ka aadha hai. "Slower hamesha greener hai" rule ko kya break karta hai? ::: Static leakage power $V\cdot I_{\text{leak}}$ poore (zyada lambe) runtime ke liye energy drain karta rehta hai, isliye ek sweet-spot frequency ke neeche total energy phir se badhne lagti hai.