Dynamic vs static power consumption — Hinglish notes

6.4.1 · Hardware › Power, Thermal & Reliability

Power Consumption Kya Hai?

Digital circuits mein Power consumption woh rate hai jis par electrical energy heat mein convert hoti hai. CMOS (Complementary Metal-Oxide-Semiconductor) circuits ke liye—jo modern CPUs, GPUs, aur SoCs ka foundation hai—power do categories mein banti hai:

Dynamic Power: Switching activity ke dauran consume hoti energy (transistors ka state 0→1 ya 1→0 mein badalna)
Static Power: Jab circuit idle ho tab consume hoti energy (leakage currents)

Kyun zaroori hai: Power directly heat mein translate hoti hai. Zyada heat hogi toh performance degrade hogi (thermal throttling), chip ki lifespan kam hogi, aur batteries drain hongi. Is split ko samajhna engineers ko performance vs battery life vs cooling ke liye optimize karne mein help karta hai.

Dynamic Power: Switching Ki Cost

First Principles Se Derivation (Switching Component)

Step 1: Capacitor Ko Charge Karne Ki Energy

Ek CMOS gate ko ek capacitor $C$ ke roop mein model kiya jaata hai jo ek transistor ke through voltage source $V_{dd}$ se connected hota hai. Jab output 0 se $V_{dd}$ par switch karta hai, capacitor charge hota hai.

Power supply se capacitor ko 0 se $V_{dd}$ tak charge karne mein li gayi energy:

$E_{supply} = \int_{0}^{Q} V d q = \int_{0}^{C V_{dd}} V_{dd} d q = V_{dd} \cdot Q = C V_{dd}^{2}$

Kyun? Supply voltage $V_{dd}$ constant hai. Capacitor par charge $Q = C V_{dd}$ push karne ke liye, supply work karta hai $W = V \cdot Q$ .

Step 2: Capacitor Mein Store Hoti Energy

Capacitor mein voltage $V_{dd}$ par stored energy:

$E_{stored} = \frac{1}{2} C V_{dd}^{2}$

Kyun? Capacitor charge hote waqt voltage linearly 0 se $V_{dd}$ tak badhta hai. Average voltage $V_{dd} /2$ hota hai, isliye $E = \frac{1}{2} Q V_{dd} = \frac{1}{2} C V_{dd}^{2}$ .

Step 3: Heat Ke Roop Mein Dissipate Hoti Energy

Charging ke dauran dissipated energy (transistor resistance mein heat ke roop mein lost):

$E_{dissipated} = E_{supply} - E_{stored} = C V_{dd}^{2} - \frac{1}{2} C V_{dd}^{2} = \frac{1}{2} C V_{dd}^{2}$

Jab transistor discharge karta hai (1→0), stored energy $\frac{1}{2} C V_{dd}^{2}$ ground mein dissipate hoti hai.

Ek switching cycle mein total energy (0→1→0):

$E_{cycle} = \frac{1}{2} C V_{dd}^{2} + \frac{1}{2} C V_{dd}^{2} = C V_{dd}^{2}$

Factor of 2 kyun? Aadha charging ke dauran lost hota hai (pull-up transistor mein), aadha discharging ke dauran (pull-down transistor mein).

Step 4: Power = Energy × Frequency

Agar gate frequency $f$ par switch karta hai (Hz mein measure hota hai, cycles per second), aur iska activity factor $α$ hai (fraction of clock cycles jisme switching hoti hai):

Physical meaning:

$V_{dd}^{2}$ : Quadratic voltage dependence—voltage aadha karne par switching power 4× kam hoti hai
$f$ : Linear frequency dependence—clock speed double karne par power double hoti hai
$α$ : Har gate har cycle switch nahi karta; typical CPUs mein low activity factors hote hain

Doosra Component: Short-Circuit Power

Standard formula yeh kyun miss karta hai: $α C V_{dd}^{2} f$ derivation sirf load capacitor ko deliver hone wale charge ko account karti hai. Short-circuit current kabhi capacitor tak nahi pahunchta—yeh input transition ke dauran directly supply→ground flow karta hai, isliye yeh ek alag term hai.

Figure — Dynamic vs static power consumption

Worked example Example 2: Battery Life Ke Liye Voltage Scaling

Ek smartphone SoC $V_{dd} = 1.2$ V par run karta hai, $P_{1} = 2.0$ W switching power consume karta hai. Battery life badhane ke liye, voltage $V_{dd} = 0.9$ V (25% reduction) kar diya jaata hai. Nayi switching power kya hogi?

$\frac{P _{2}}{P _{1}} = (\frac{V _{2}}{V _{1}})^{2} = (\frac{0.9}{1.2})^{2} = (0.75)^{2} = 0.5625$ $P_{2} = 0.5625 \times 2.0 = 1.125 W$

Yeh step kyun? Switching power $V^{2}$ ke proportional hoti hai. Frequency aur capacitance change nahi hoti, isliye ratio purely voltage squared hai.

Insight: 25% voltage drop se 44% power reduction milti hai! Isliye Dynamic Voltage and Frequency Scaling (DVFS) power management ke liye itna effective hai. Short-circuit power aur bhi tezi se girti hai ( $V_{dd} - 2 V_{t h}$ mein cubic hai), isliye low-voltage operation mein shoot-through almost khatam ho jaata hai. (Kam voltage ke saath timing margins maintain karne ke liye frequency bhi kam karni padti hai, isliye real savings utni dramatic nahi hoti lekin phir bhi significant hoti hain.)

Static Power: Leakage Tax

Leakage Ke Sources

Subthreshold leakage: Drain se source mein current flow hoti hai jab bhi $V_{g s} < V_{t h}$ ho (gate voltage threshold se neeche). Threshold voltage par exponentially dependent.
Gate oxide tunneling: Electrons thin gate oxide ke through tunnel karte hain (quantum effect). ~2 nm se neeche oxide thickness shrink hone par aur bura hota hai.
Junction leakage: p-n junctions (drain/source se substrate tak) mein reverse-bias current.

Formula

Aur detail mein (subthreshold dominant):

$I_{leakage} \propto I_{0} \cdot e^{\frac{V _{g s} - V _{t h}}{n V _{T}}} \cdot (1 - e^{- \frac{V _{d s}}{V _{T}}})$

Jahan:

$V_{t h}$ = threshold voltage
$V_{T} = k T / q \approx 26$ mV room temperature par (thermal voltage)
$n$ = subthreshold slope factor (~1.3–1.5)

Exponential kyun? Subthreshold conduction semiconductors mein diffusion current ki physics follow karta hai, jo voltage par exponentially dependent hai.

Temperature dependence: Leakage current temperature mein har 10°C badhne par roughly double ho jaata hai. High temperatures static power ke liye catastrophic hain.

Total Power Consumption

Design tradeoffs:

Low power (mobile): $V_{dd}$ kam karo (switching quadratically help karta hai, short-circuit cubically, static linearly), $f$ kam karo, high- $V_{t h}$ transistors use karo (kam leakage lekin slow), unused blocks power-gate karo
High performance (datacenter): High power accept karo, cooling maximize karo, low- $V_{t h}$ transistors use karo (fast lekin leaky)

Dynamic vs Static: Historical Shift

Era	Process Node	Dominant Power	Kyun
1990s–2000s	>130 nm	Dynamic	Thick oxides → low leakage, high voltages → high switching energy
2000s–2010s	90–45 nm	Transition	Gate oxide thinning → tunneling badhta hai
2010s–ab	<22 nm	Dono comparable	FinFETs leakage kam karte hain lekin billions transistors matlab static bhi add up hoti hai

FinFET improvement: 3D gate structure electrostatic control improve karta hai → same performance ke liye kam leakage. Lekin jaise hum aur transistors pack karte hain, total static power phir bhi badhti rehti hai.

Common mistake Common Mistake: "Dynamic Power SIRF α·C·V²·f Hai"

Galat intuition: "Famous formula saari switching power capture karta hai."

Sahi kyun lagta hai: Yeh har textbook ki headline mein hai aur total mein dominate karta hai, isliye assume karna easy hai ki yeh complete hai.

Reality: $α C V_{dd}^{2} f$ sirf load capacitor ko deliver hone wale charge ko count karta hai. Har transition ke dauran, PMOS aur NMOS dono briefly conduct karte hain, ek direct $V_{dd}$ →ground short-circuit current create karte hain jo capacitor ko kabhi touch nahi karta. Yeh ek alag 5–15% term add karta hai.

Fix: $P_{dynamic} = P_{switching} + P_{short-circuit}$ likho. Short-circuit power ko sharp input edges (chhota transition time $τ$ ) se aur $V_{dd} ≲ 2 V_{t h}$ ke paas operate karke minimize karo jahan yeh vanish ho jaata hai.

Recall Feynman Explanation (Ek 12-Saal Ke Bacche Ko Explain Karo)

Socho tumhare paas ek dabba light switches ka hai. Har baar jab tum switch on ya off karte ho, use push karna padta hai—usme muscle energy lagti hai. Jitna tezi se switches flip karte ho, utna thak jaate ho. Yeh hai switching power: cheezein change karne ki energy.

Ek chhupi hui extra cost bhi hai: jab tum switch flip karte ho, ek chhote se instant ke liye woh na fully on hota hai na fully off—beech mein hota hai. Uss instant mein, electricity battery se directly ground tak shortcut le leti hai aur heat ke roop mein waste ho jaati hai. Yeh hai short-circuit power—ek chhota sa leak jo flip ke dauran hota hai.

Aur ek aur baat: jab switch "off" hota hai, tab bhi woh perfectly off nahi hota. Yeh uss door ki tarah hai jo theek se band nahi hoti—light crack se leak hoti hai. Tumhare saare switches idle hone par bhi thoda sa leak karte hain. Yeh hai static power.

Purane switches mein (bade chunky wale), leaks itni chhoti thi ki ignore kar sakte the. Lekin modern computer switches super tiny hote hain—ek germ se bhi chhote. Uss size par, electricity itni "slippery" hoti hai ki switch band hone par bhi leak ho jaati hai. Power save karne ke liye: switches slow flip karo, kam voltage use karo, unhe crispy flip karo (kam shortcut waste), aur jo switches use nahi ho rahe unhe unplug karo. Isliye phones din bhar chalte hain aur servers ko giant fans chahiye hote hain.

Connections

CMOS Inverter Design: Dynamic power derivation ka foundation aur jahan short-circuit current arise hoti hai
Capacitance in VLSI: $C$ kahan se aata hai (gate, wire, load)
Thermal Design Power (TDP): $P_{total}$ kaise cooling requirements set karta hai
Dynamic Voltage Frequency Scaling (DVFS): Power optimize karne ke liye voltage/frequency knobs use karna
Power Gating Techniques: Idle blocks mein static power cut karna
FinFET Transistors: 3D gates leakage kaise kam karte hain
Subthreshold Slope: Physics jo batati hai ki leakage exponential kyun hai
Signal Transition Time: Sharp edges short-circuit power minimize karti hain
Amdahl's Law: Kyun sab kuch off nahi kar sakte (parallelism vs power)

#flashcards/hardware

CMOS circuits mein power consumption ki do categories kya hain? :: Dynamic power (switching + short-circuit) aur static power (leakage).

Dynamic power ke do components kya hain?

(1) Load capacitance charge/discharge karne se switching power (

α C V_{dd}^{2} f

), aur (2) transition ke dauran dono transistors brief time ke liye conduct karne se short-circuit (shoot-through) power.

Switching power formula aur har term ka matlab :: $P_{switching} = α C V_{dd}^{2} f$ , jahan $α$ activity factor hai, $C$ capacitance hai, $V_{dd}$ supply voltage hai, $f$ frequency hai.

α C V^{2} f

formula saari dynamic power kyun capture nahi karta?

Yeh sirf load capacitor ko deliver hone wale charge ko account karta hai. Yeh short-circuit current miss karta hai jo transition ke dauran PMOS aur NMOS dono conduct karne par directly

V_{dd}

se ground tak flow karta hai.

Short-circuit (shoot-through) power kya cause karta hai?

Finite-time input transition ke dauran, pull-up (PMOS) aur pull-down (NMOS) dono transistors momentarily ON hote hain,

V_{dd}

se ground tak ek direct conducting path create karte hain.

Short-circuit power kaise minimize karo?

Sharp input edges use karo (chhota transition time

τ

), rise/fall times balance karo, aur jahan

V_{dd} ≲ 2 V_{t h}

ho wahan operate karo (short-circuit vanish ho jaata hai kyunki dono transistors ek saath threshold exceed nahi kar sakte).

Switching power

V_{dd}

ki jagah

V_{dd}^{2}

ke saath kyun scale hoti hai?

Capacitor charge karne ki energy

C V_{dd}^{2}

hai (ek factor charge

Q = C V_{dd}

se, ek voltage se). Aadha charge ke dauran lost hota hai, aadha discharge ke dauran, isliye per cycle

C V_{dd}^{2}

hota hai. Power = energy × frequency.

Activity factor

α

kya hai aur typical values kya hain?

Fra