Visual walkthrough — IP cores and SoC bus fabric

This page rebuilds the parent's central result — the crossbar complexity formula $\text{switches}=N\times M$ — from absolutely nothing. We start with two chips that want to talk, and we grow the picture, one wire at a time, until the number $N\times M$ falls out on its own.

You do not need to know what a "bus", "master", or "arbiter" is. We define each the instant it is needed, and we draw it.

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Step 1 — Two blocks, one wire: what "talking" even means

WHAT. Put one master (call it $M_1$) on the left and one slave ($S_1$) on the right. Draw a single line between them.

WHY. Before counting many wires, we must agree what one connection is. A connection is any physical path over which a request can flow from a master to a slave. One master, one slave → exactly one path needed.

PICTURE. The blue box is the master, the green box is the slave, the yellow line is the one path that lets $M_1$ reach $S_1$.

$$\text{paths}=\underset{\text{masters}}{\underbrace{1}}\times \underset{\text{slaves}}{\underbrace{1}}=1$$

• The first $1$ counts how many blocks can start a conversation.
• The second $1$ counts how many blocks can answer.
• Their product counts the master–slave pairs that might ever need to touch — here, just one.

Hold onto that word pair. The whole formula is really a count of pairs.

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Step 2 — Add a second slave: one master, two destinations

WHAT. Keep $M_1$. Add a second slave $S_2$ (say, a UART, while $S_1$ is RAM). Now $M_1$ might want either one.

WHY. A real CPU talks to many things: memory, a timer, a serial port. Each is a separate slave at a separate address. If $M_1$ must be able to reach both, it needs a path to each.

PICTURE. Two yellow lines leave $M_1$ — one to $S_1$, one to $S_2$. The little diamond where a line meets a slave is a switch: a gate that is either open (this path carries the current transaction) or closed.

$$\text{paths from }{M}_1=\underset{M_1}{\underbrace{1}}\times \underset{S_1,S_2}{\underbrace{2}}=2$$

• $1$ = the single master doing the asking.
• $2$ = the number of doors ($S_1$, $S_2$) it might knock on.
• Product $=2$ switches, because each door needs its own gate.

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Step 3 — Add a second master: now paths can happen at the same time

WHAT. Add master $M_2$ (a DMA engine — a block that copies memory without the CPU, see DMA). Give it its own pair of lines, one to each slave.

WHY — the key idea. In a simple bus only one master may speak at a time; if the CPU is using the wire, the DMA waits. A crossbar instead gives every master its own set of wires so two conversations can run concurrently — $M_1\to S_1$ while $M_2\to S_2$. That parallelism is the entire reason we spend the extra switches.

PICTURE. Two blue masters on the left, two green slaves on the right. Every master has a line to every slave. Count the diamonds: there are four.

$$\text{switches}=\underset{N=\text{masters}}{\underbrace{2}}\times \underset{M=\text{slaves}}{\underbrace{2}}=4$$

• $N$ = number of masters (rows in the grid).
• $M$ = number of slaves (columns in the grid).
• Why multiply? For each of the $N$ masters we lay down $M$ switches (Step 2 gave $M$ switches per master). Doing that $N$ times stacks $N$ identical rows → $N\times M$ total. Multiplication is just "$N$ copies of $M$."

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Step 4 — The collision problem: two masters, one slave

WHAT. Let both $M_1$ and $M_2$ want $S_1$ in the same clock cycle.

WHY. Two switches into $S_1$ are open at once → two masters shove data onto $S_1$'s single input at the same instant. That is an electrical fight; the data is garbage. We need a referee.

PICTURE. Both masters aim at $S_1$ (red = the conflict). A red arbiter block sits on $S_1$'s door and lets exactly one through; the other's request is held.

How many arbiters? A collision can only happen at a slave (that is where paths converge). So we need one arbiter per slave:

$$\text{arbiters}=\underset{\text{one per slave}}{\underbrace{M}}$$

Same reasoning names the address comparators: each slave owns a range of addresses, and something must check "is this request's address mine?" — one comparator per slave, also $M$.

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Step 5 — The general grid: reading off all three counts

WHAT. Redraw with general $N$ masters and $M$ slaves. Label the rows $M_1\dots M_N$ and columns $S_1\dots S_M$.

WHY. Steps 1–4 built every piece on tiny examples. Now we just read the grid to get the parent's formula for any size.

PICTURE. A full $N\times M$ lattice. Every crossing is a switch (blue). The bottom of every column carries one arbiter + one address comparator (red).

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Step 6 — Why it stops working: the $N\times M$ growth curve

WHAT. Plot switch count as $N$ and $M$ grow together (say $N=M=n$, so switches $=n^2$).

WHY. The parent says flat crossbars "don't scale beyond ~10–20 ports." Here is why in one picture: doubling the ports quadruples the switches. Cost climbs as area, not as length.

PICTURE. The blue curve $n^2$ (crossbar) rockets past the yellow line $n$ (a single shared bus). At $n=20$ that is $400$ switches on the chip — the point where designers switch to a hierarchical topology or a Network-on-Chip.

$$\text{switches}(n)=n\times n=n^2⟹\text{switches}(2n)=(2n{)}^2=4n^2$$

• $n^2$ is the count on the square grid.
• Replacing $n$ by $2n$ gives $4n^2$: four times the switches for two times the ports. That quadratic blow-up is the wall.

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Step 7 — The degenerate cases: check the corners

Every honest derivation must survive its extremes. Feed the formula tiny/empty inputs.

Case	$N$	$M$	switches $=N\times M$	Does the picture agree?
Nobody talks	$0$	any	$0$	No masters → no wires. ✔
Nothing to talk to	any	$0$	$0$	No slaves → no destinations. ✔
One-to-one link	$1$	$1$	$1$	Exactly Step 1's single wire. ✔
Single shared bus	$N$	$M$ but 1 path	(bus shares 1 wire, not $NM$)	Cheaper, but only 1 transaction at a time — Step 3's parallelism is gone.

The formula degrades gracefully: set either factor to $0$ and you correctly get $0$ switches — no special-casing required.

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The one-picture summary

One master–slave pair (Step 1) → a row of $M$ switches for one master (Step 2) → stack $N$ such rows for a full grid of $N\times M$ switches (Step 3) → hang one arbiter under each of the $M$ columns to settle collisions (Step 4) → read off all costs (Step 5) → and watch the count explode as $n^2$ so we know when to stop (Step 6).

Recall Feynman retelling — say it back in plain words

Picture blocks that ask on the left and blocks that answer on the right. If one asker must reach several answerers, it needs one little on/off gate — a switch — for each answerer. Line up all the askers as rows and all the answerers as columns; wherever a row crosses a column you drop a switch. So the number of switches is just rows times columns: $N$ times $M$. When two askers grab the same answerer, they collide, so each answerer keeps a referee (an arbiter) at its door — one referee per column, giving $M$ of them. The whole thing is a rectangle: rows $\times$ columns squares. That is why the cost grows like the area of the rectangle, and why doubling everything quadruples the switches — which is exactly when engineers give up on the flat grid and build something smarter.

Recall

How many switches does a full crossbar of $N$ masters and $M$ slaves need? ::: $N\times M$ — one per (master, slave) pair. Why one arbiter per slave and not per master? ::: Collisions happen only where paths converge — at a slave — so each slave (column) needs its own referee, giving $M$ arbiters. What do the extra $N\times M$ switches buy over a single shared bus? ::: Concurrency — $M_1\to S_1$ can run at the same time as $M_2\to S_2$. If you double both $N$ and $M$, how does the switch count change? ::: It quadruples, because $(2n{)}^2=4n^2$.

Related: Interconnect Topologies · Cache Coherence Protocols · Memory-Mapped I/O · DMA · PCIe