Intuition The one core ideaAn SoC is a tiny city where pre-built factories (IP cores) send parcels to each other along a shared road system (the bus fabric). Everything in this topic is about who can send a parcel, to which address, and how many roads exist so nobody has to wait.
This page assumes you have seen nothing . Before you meet a single AXI channel or crossbar formula in the parent note , you must own every word and symbol it throws at you. We build them one at a time, each on top of the last.
A chip is a single flat sliver of silicon holding millions of tiny switches (transistors). Picture a city seen from above : one big rectangular plot of land.
Definition Functional blockA functional block is a region of that chip that does one job — for example "do arithmetic" or "talk to memory". Picture one building inside the city.
If we drew a wire from every building to every other building by hand, the city would be nothing but tangled roads. That tangle is exactly the problem this topic solves — so hold that picture.
Look at the left panel: buildings with private wires between every pair — chaos that grows fast. The right panel replaces them with one shared road every building taps into. That shared road is the seed of a bus .
IP stands for Intellectual Property . An IP core is a functional block that someone already designed and tested , which you license and drop into your chip — like buying a pre-fabricated building instead of laying every brick yourself.
Why does the topic need this word? Because the whole point of an SoC is reuse . You do not design a USB controller from scratch; you buy the "USB building" and place it.
The parent note grades IP cores by how finished the building is when it arrives :
Word
Plain meaning
Picture
Soft IP arrives as source text (Verilog/VHDL) you still shape
architect's blueprint — reshape freely
Firm IP arrives as a gate netlist (a wiring list of logic gates)
pre-cut lumber — some shape fixed
Hard IP arrives as a fixed physical layout (exact transistor positions)
finished concrete building — cannot move a wall
Intuition Soft → Firm → Hard is a flexibility/performance tradeThe more finished the building arrives, the faster and smaller it runs — but the less you can change it. Soft = most freedom, worst optimisation. Hard = best performance, zero freedom.
Two words above need their own definitions before we go on.
Definition RTL and Verilog/VHDLRTL (Register Transfer Level) is a way of describing hardware as "on each clock tick, move this data into that storage box". Verilog and VHDL are the two languages people write RTL in. Picture a recipe that says what happens every tick, not a physical object yet.
A netlist is a plain list saying "gate A's output wire connects to gate B's input wire". Picture a connect-the-dots sheet : the dots (gates) and which lines join them, but not yet placed on the ground.
Definition Gate-level / GDSII / layoutA gate is the smallest logic unit (AND, OR, NOT). GDSII is the file format that stores the final physical layout — the exact shapes and positions of every transistor. Picture the finished street map with every building nailed to its plot.
Every communication needs a starter and a responder . Hardware uses two blunt words.
Definition Master and SlaveA master is a block that starts a transaction ("I want to read/write"). A slave is a block that only responds when asked. Picture a customer (master) walking up to a shop counter (slave): the customer speaks first.
Common mistake A block can be bothA DMA engine is a slave when the CPU configures it, then becomes a master when it moves data on its own. "Master/slave" is a role in one transaction , not a permanent label.
A transaction is one complete request-and-answer: an address goes out, data moves, an acknowledgement comes back. Picture the whole exchange at the counter — ask, hand over goods, get a receipt.
The parent note names three common master IPs and their jobs — link them so you know what each building actually does:
DMA — a mover that shuttles data without bothering the CPU.DRAM Controllers — the building that talks to main memory chips.PCIe — a high-speed link to devices outside the chip.
An address is a number that names a location a master wants to reach. Picture a street number on the shared road. Different slaves own different ranges of numbers.
Definition Address decodingAddress decoding is comparing the address on the road against each slave's number range to decide which slave should answer . Picture the road's traffic sign: "numbers 0x1000–0x1FFF → turn right to RAM".
Routing is actually steering the parcel down the chosen path once decoding picked the door. Picture the junction that physically opens the gate toward RAM.
The idea that "a location number tells hardware which block responds" has its own name in the vault: Memory-Mapped I/O . Every peripheral pretends to be a stretch of memory addresses.
The figure shows one address 0x1400 entering the decoder. Each slave carries a range sign; the decoder lights up the one slave whose range contains 0x1400 (the pink RAM), and routing opens that path only.
A bus is the shared set of wires many blocks tap into. Picture the single main road . Its weakness: only one parcel can travel at a time.
If two masters both want the road on the same tick, someone must referee.
Arbitration is the referee that picks which master goes first when several want the same resource at once. Picture a traffic cop at the junction holding one car while another passes.
Now the key upgrade the whole topic is built around:
A bus fabric is a road network , not a single road: many parallel paths plus decoders and arbiters, so several transactions run at the same time . Picture a grid of streets with traffic cops at each crossing instead of one shared lane.
A crossbar is the simplest full fabric: a physical grid where every master's row can connect to every slave's column at a crosspoint switch . Picture graph paper — rows are masters, columns are slaves, and each intersection is a switch you can close.
Count the closed switches (yellow dots) in the figure: master M1 reaches slave S3 while M2 independently reaches S1 — two parcels, same instant . That parallelism is impossible on a single bus. The grid of dots is why the parent's formula counts N × M
Two more words the parent uses freely:
Definition N, M, and the × symbolN number of masters , M number of slaves . The symbol × N × M area of the grid : N M
Worked example Plug in the parent's numbersWith N = 4 M = 8 4 × 8 = 32 8 8 product , which is why huge SoCs stop using one flat grid.
The vault has a whole page on the shapes these networks take: Interconnect Topologies .
O ( ⋅ ) O ( N × M ) grows in proportion to N × M area of a rectangle getting wider and taller. The parent uses it to warn that flat crossbars explode past ~10–20 ports.
Why this tool and not a plain number? Because we care about the trend , not one instance — Big-O answers "will this still work when the chip doubles in size?" A single number can't answer that; a growth law can.
Definition Clock and cycleA clock is a signal that ticks on and off at a fixed rate. One cycle is one tick. MHz (megahertz) counts millions of ticks per second, so 100 MHz = 100 million cycles each second . Picture a metronome : every beat is a chance for data to move one step.
Definition Bit, byte, and their symbolsA bit is one 0-or-1. A byte is 8 bits. "32-bit data" means 32 wires carry data at once. Picture 32 parallel lanes , each carrying one 0/1 per beat.
Throughput is how much data moves per second . Its recipe: bits-per-transfer, divided by cycles-per-transfer, times ticks-per-second.
Throughput = cycles per transfer bits per transfer × clock rate
Worked example Rebuild the parent's APB numberAPB needs 2 cycles per transfer of 32 bits at 100 MHz:
2 cycles 32 bits × 100 000 000 /s = 1.6 × 1 0 9 bit/s = 1.6 Gb/s = 200 MB/s 1.6 Gb/s = 200 MB/s
Pipelining means starting the next job before the current one fully finishes, like an assembly line. Picture a laundromat : you start washing load 2 while load 1 dries, instead of waiting.
A burst is sending one address, then many data words back-to-back. Picture giving the postman one street number and handing over four parcels — no need to repeat the address four times.
A channel is a dedicated set of wires for one kind of traffic . AXI splits work into 5 channels (write-address, write-data, write-response, read-address, read-data). Picture five separate conveyor belts , so an address can travel while data on another belt keeps flowing — the parent's whole "parallelism" argument rests on this.
Recall Why separate address and data channels?Because their timings differ — the slave can accept an address and prepare while the master is still gathering the data. Separate belts let both happen at once instead of one blocking the other.
Definition QoS (Quality of Service)QoS is a priority scheme : important traffic (live video) gets the road before unimportant traffic (a background copy). Picture an ambulance lane — the arbiter always waves the ambulance through first. Related on-chip concern: Power Management often shares this arbitration logic to slow idle blocks.
One more prerequisite word the parent leans on when many masters share memory:
Definition Coherence (preview)Cache coherence is keeping copies of the same data consistent when several masters cache it. You only need to know it exists here; the deep treatment lives in Cache Coherence Protocols .
chip and functional block
pipelining bursts channels
Cover the right side and test yourself. If any answer is fuzzy, re-read its section.
What is an IP core, in one line? A pre-designed, pre-tested functional block you license and drop into a chip — a pre-fab building.
Soft vs Hard IP — which is more flexible, which is faster? Soft is most flexible (source text you reshape); Hard is fastest/smallest (fixed physical layout).
Who speaks first, master or slave? The master — it starts the transaction; the slave only responds.
What does address decoding decide? Which slave owns the address, so the request is routed to the correct door.
Why does a plain bus limit performance? Only one transaction can use the single shared road at a time.
What does a bus fabric add over a bus? Parallel paths plus decoders and arbiters, so several transactions run simultaneously.
How many switches does an N×M crossbar need, and why? N × M — one crosspoint switch for every master–slave pair (area of the grid).
What does O ( N × M ) Cost grows in proportion to the product N·M, so flat crossbars explode as the SoC scales.
Write the throughput formula. (bits per transfer ÷ cycles per transfer) × clock rate.
Why does AXI use 5 separate channels? Dedicated wires per traffic type let address, data, and response flow in parallel (pipelining).
What is a burst? One address followed by many data words back-to-back, amortising the address overhead.
What does QoS provide on the fabric? Priority arbitration so time-critical traffic wins the road over low-priority traffic.
