Exercises — IP cores and SoC bus fabric

A GDSII file (the format that stores a chip's final physical layout — the exact shapes of every transistor and wire) with placed transistors is a physical layout, so this is a hard IP core. Why: the three flavours form a ladder of "how baked is it?"

• Soft = RTL source (Verilog) → most flexible, you synthesise it yourself.
• Firm = gate-level netlist → partly baked.
• Hard = physical layout (GDSII) → fully baked to one process. Because a hard core's transistors are already placed and sized for one specific process node, you cannot re-target it. That rigidity is the price you pay for its best-in-class speed/area. See DRAM Controllers — the DDR PHY is the classic hard-IP example because it contains analog timing circuits that must be hand-tuned.

The Write Response channel (B), flowing Slave → Master. The five channels split by job and direction:

• AW, W → master to slave (address & data for writes)
• B → slave to master (write acknowledgement)
• AR → master to slave (read address)
• R → slave to master (read data + response) The acknowledgement the question describes is the slave saying "done, here's the status (OKAY/error)", so it must travel back to the master on B. (This is a distinct protocol from PCIe, which is a serial link, not an on-chip AXI fabric — do not confuse the two.)

Use the crossbar-complexity rules with $N=6$ masters and $M=10$ slaves. $\text{Switches}=N\times M=6\times 10=60$ Why $N\times M$: every master must be able to reach every slave, so each (master, slave) pair gets its own crosspoint — count the grid intersections. Look at Figure s01: each lavender master row crosses each mint slave column, and a coral dot sits at every intersection — that dot is a crosspoint switch. Count the dots and you count the switches. $\text{Arbiters}=M=10$ Why one per slave: all 6 masters could target the same slave at once, so each slave needs a referee to pick one winner. $\text{Address comparators}=M=10$ Why one per slave: each slave owns an address range; a comparator per slave checks "is this transaction's address inside my range?" for routing.

Figure s01 — a 3×4 grid is drawn for legibility; the arithmetic in the caption scales it to the exercise's 6×10 = 60 switches, 10 arbiters, 10 comparators.

Throughput = (bits moved per transfer) ÷ (cycles per transfer) × (clock rate). $\text{Throughput}=\frac{32\text{bits}}{2\text{cycles}}\times 50\times 10^6\text{Hz}=800\times 10^6\text{bit/s}$ Convert to bytes (÷8): $800\times 10^6/8=100\times 10^6$ bytes/s $=100$ MB/s. Why the ÷2: APB is non-pipelined, so every single transfer always pays the SETUP cycle plus the ACCESS cycle — no overlap. That fixed 2-cycle tax is exactly why APB is reserved for slow peripherals (GPIO, timers) where 100 MB/s is plenty.

$\text{AHB}=\frac{32}{1}\times 100\times 10^6=3.2\times 10^9\text{bit/s}=400\text{MB/s}$ $\text{APB}=\frac{32}{2}\times 100\times 10^6=1.6\times 10^9\text{bit/s}=200\text{MB/s}$ Ratio $=400:200=2:1$. What the pipeline bought: AHB overlaps the address phase of the next transfer with the data phase of the current one, so after the pipeline fills it delivers one transfer every single cycle instead of every two — exactly doubling throughput at the same clock.

Failure 1 — no parallelism. With one transaction at a time, while the DMA holds the bus, the CPU is frozen even if it wants a totally different slave. → demands parallel data paths (a crossbar) so CPU→S1 and DMA→S2 run at once. Failure 2 — no QoS/priority. Even with parallelism, if both target the same slave, a long DMA burst can starve the time-critical video. → demands QoS-aware arbitration so the arbiter can preempt/prioritise the CPU. Key insight: these are orthogonal problems. Parallelism fixes "different destinations collide"; arbitration+QoS fixes "same destination, unequal urgency". A good fabric needs both. Contrast with Cache Coherence Protocols, which solve a third, separate problem — keeping duplicated data consistent — not covered by either feature above.

(a) In $L+2$ cycles we move $32L$ bits: $\text{Throughput}(L)=\frac{32L}{L+2}\times 100\times 10^6\text{bit/s}$ (b) For $L=16$: numerator $32\times 16=512$ bits over $16+2=18$ cycles: $\frac{512}{18}\times 100\times 10^6\approx 2.844\times 10^9\text{bit/s}\approx 355.6\text{MB/s}$ (c) With 4 bursts in flight, the overhead of one hides behind the data of another, so throughput scales ~linearly: $\approx 4\times 355.6\approx 1422\text{MB/s}\approx 1.42\text{GB/s}$ Why overlap works: AXI's split channels let the master issue address #2 while data #1 is still streaming — the fixed 2-cycle tax is paid in parallel across transactions, so it stops mattering once several are outstanding. Look at Figure s02: the top row shows one lonely burst paying its two butter-coloured overhead cells (AR and R) around its data. The stacked rows below show three bursts staggered in time — the "A" overhead of the next burst runs while the previous burst's data is still streaming, which is exactly why the tax disappears. This is the whole reason AXI beats AHB despite similar per-burst numbers.

Figure s02 — time runs left to right; overlapping the fixed overhead is what lifts effective throughput toward 4× the single-burst figure.

Choose a single shared bus (APB-style). Switch count: a crossbar for $N=1$ master, $M=3$ slaves needs $1\times 3=3$ switches, $3$ arbiters, $3$ comparators — but with only one master there is never contention, so parallelism buys nothing. The extra switches are pure waste. Power angle: every crosspoint switch, arbiter and comparator is logic that leaks static power and toggles dynamically. For a low-power node you strip out all logic that earns no benefit. A single shared bus is minimal-gate → minimal leakage → longest battery life. Rule of thumb: crossbars pay off only when you have multiple masters wanting different slaves simultaneously. One master ⇒ no parallelism to exploit ⇒ shared bus.

(a) Flat crossbar: $N=8$, $M=16$. $\text{Switches}=8\times 16=128,\text{Arbiters}=16,\text{Comparators}=16$ (b) Hierarchical. The fast crossbar sees 4 masters and (4 fast slaves + 1 APB-bridge port) $=5$ slave ports: $\text{Fast-crossbar switches}=4\times 5=20$ The APB bridge behind that single port fans out to 12 slow slaves on a shared bus — 0 extra crosspoint switches (shared bus, not a crossbar). $\text{Total crosspoint switches}=20+0=20$ That is a drop from 128 → 20, roughly a 6.4× reduction in crosspoint switches. (c) Trade-off: we traded parallel access to the slow slaves (now serialised behind one APB bridge) for a massive cut in switch/area/power — acceptable precisely because slow peripherals rarely need concurrent high-bandwidth access. Look at Figure s03: the four lavender masters feed a single AXI crossbar block; on its right, four mint fast-slaves each get a direct crossbar port, while the coral APB bridge is one port that fans the 12 grey slow slaves onto a shared bus (no crosspoints). The caption arithmetic shows the 4×5 = 20 versus the flat 8×16 = 128.

Figure s03 — collapsing many slow slaves behind one bridge port is the core trick of hierarchical (Network-on-Chip-style) fabrics.

False. Burst mode does not reduce first-word latency. The address phase (AW/AR handshake) still has to complete before any data arrives, so the time to the first word is unchanged whether the burst is length 1 or length 16. What burst actually improves: throughput (bytes per second averaged over the transfer). By sending one address for $L$ data beats, it amortises the fixed address/response overhead across many words — so the average cost per word drops, even though the first word's latency is fixed. Master principle: latency = "time to first byte"; throughput = "bytes per second at steady state". Bursts and pipelining are throughput tools; they leave the initial handshake latency alone. Confusing the two is the single most common fabric-analysis error.

A block that starts a transaction is a master; one that answers is a slave. Full-crossbar switch count for $N$ masters, $M$ slaves ::: $N\times M$ Number of arbiters in a full crossbar ::: $M$ (one per slave) Which AXI channel carries the write acknowledgement, and which way ::: The B (Write Response) channel, slave → master Burst mode improves throughput, and leaves first-word latency unchanged. APB is non-pipelined and costs 2 cycles per transfer. AXI, AHB and APB all belong to which ARM family ::: AMBA (Advanced Microcontroller Bus Architecture)