IP cores and SoC bus fabric: Exercises — Hinglish deep dive

6.3.10 · D4 · Hardware › Interconnects, Buses & SoC › IP cores and SoC bus fabric

Shuru karne se pehle, ek simple glossary taaki koi symbol "free mein" na aaye. Ek SoC (System-on-Chip) ek poora computer hai jo silicon ke ek tukde par squeeze kiya gaya hai. Iske andar ke reusable blocks (ek CPU, ek memory controller, ek USB block) IP cores hain — pre-built LEGO pieces. Woh wiring jo in pieces ko aapas mein baat karne deti hai, woh bus fabric hai. Ek master woh block hai jo conversation shuru karta hai (read/write karne ko kehta hai). Ek slave woh block hai jo jawab deta hai (memory, ek peripheral register). In dono words ko theek se yaad rakho — fabric maths ka aadha hissa sirf yeh hai ki "bahut se puuchne wale bahut se jawab dene walon tak kaise pahunchen".

Definition Teen ARM bus names, ek baar clearly bataye gaye

ARM ki fabric family ko AMBA (Advanced Microcontroller Bus Architecture) kehte hain. Iske teen members hain jo is page par milenge:

AXI = Advanced eXtensible Interface — yeh high-performance wala hai, 5 independent channels aur burst transfers ke saath.
AHB = Advanced High-performance Bus — mid-tier, pipelined address/data ek single shared channel par.
APB = Advanced Peripheral Bus — sabse simple, non-pipelined, slow peripherals ke liye. Yeh bhi jaanna useful hai: GDSII = Graphic Data System II, woh file format jo chip ki final physical layout store karta hai (har transistor aur wire ki actual shapes). Jab koi block GDSII ke roop mein ship hota hai, uske transistors already placed hote hain — woh ek process ke liye fully baked hai.

Level 1 — Recognition

Recall Solution

Ek GDSII file (woh format jo chip ki final physical layout store karta hai — har transistor aur wire ki exact shapes) jisme transistors placed hain, woh ek physical layout hai, isliye yeh ek hard IP core hai. Kyun: teen flavours "kitna baked hai?" ki ek ladder banate hain:

Soft = RTL source (Verilog) → sabse flexible, tum khud synthesise karte ho.
Firm = gate-level netlist → partly baked.
Hard = physical layout (GDSII) → ek process ke liye fully baked. Kyunki ek hard core ke transistors already placed aur ek specific process node ke liye sized hain, tum ise re-target nahin kar sakte. Yeh rigidity woh price hai jo tum iske best-in-class speed/area ke liye chukate ho. Dekho DRAM Controllers — DDR PHY classic hard-IP example hai kyunki isme analog timing circuits hoti hain jo hand-tune karni padti hain.

Recall Solution

Write Response channel (B), Slave → Master direction mein flow karta hai. Paanch channels kaam aur direction se split hote hain:

AW, W → master se slave ko (writes ke liye address & data)
B → slave se master ko (write acknowledgement)
AR → master se slave ko (read address)
R → slave se master ko (read data + response) Question mein jo acknowledgement describe ki gayi hai, woh slave ka yeh kehna hai "ho gaya, yeh raha status (OKAY/error)", isliye woh wapas master ko B par jaani chahiye. (Yeh PCIe se alag protocol hai, jo ek serial link hai, on-chip AXI fabric nahin — dono ko confuse mat karo.)

Level 2 — Application

Recall Solution

Crossbar-complexity rules use karo jahan $N = 6$ masters aur $M = 10$ slaves hain. $Switches = N \times M = 6 \times 10 = 60$ $N \times M$ kyun: har master ko har slave tak pahunchne ki capability honi chahiye, isliye har (master, slave) pair ko apna crosspoint milta hai — grid ke intersections count karo. Figure s01 dekho: har lavender master row har mint slave column ko cross karti hai, aur ek coral dot har intersection par baitha hai — woh dot hi ek crosspoint switch hai. Dots count karo aur switches count karo. $Arbiters = M = 10$ Ek per slave kyun: saare 6 masters ek hi slave ko target kar sakte hain ek saath, isliye har slave ko ek referee chahiye jo ek winner chunega. $Address comparators = M = 10$ Ek per slave kyun: har slave ek address range own karta hai; ek comparator per slave yeh check karta hai "kya is transaction ka address meri range mein hai?" routing ke liye.

Figure s01 — padh'ne ki ease ke liye ek 3×4 grid draw ki gayi hai; caption mein arithmetic ise exercise ke 6×10 = 60 switches, 10 arbiters, 10 comparators tak scale karta hai.

Recall Solution

Throughput = (bits moved per transfer) ÷ (cycles per transfer) × (clock rate). $Throughput = \frac{32 bits}{2 cycles} \times 50 \times 1 0^{6} Hz = 800 \times 1 0^{6} bit/s$ Bytes mein convert karo (÷8): $800 \times 1 0^{6} /8 = 100 \times 1 0^{6}$ bytes/s $= 100$ MB/s. ÷2 kyun: APB non-pipelined hai, isliye har single transfer hamesha SETUP cycle plus ACCESS cycle pay karta hai — koi overlap nahin. Yeh fixed 2-cycle tax exactly wahi reason hai ki APB slow peripherals (GPIO, timers) ke liye reserved hai jahan 100 MB/s kaafi hai.

Level 3 — Analysis

Recall Solution

$AHB = \frac{32}{1} \times 100 \times 1 0^{6} = 3.2 \times 1 0^{9} bit/s = 400 MB/s$ $APB = \frac{32}{2} \times 100 \times 1 0^{6} = 1.6 \times 1 0^{9} bit/s = 200 MB/s$ Ratio $= 400 : 200 = 2 : 1$ . Pipeline ne kya diya: AHB agle transfer ke address phase ko current transfer ke data phase ke saath overlap karta hai, isliye pipeline fill hone ke baad woh har do ke bajaye har ek cycle mein ek transfer deliver karta hai — same clock par throughput exactly double ho jaata hai.

Recall Solution

Failure 1 — koi parallelism nahin. Ek time par ek transaction ke saath, jab DMA bus hold kare, CPU frozen hai chahe woh bilkul alag slave chahta ho. → demand parallel data paths (ek crossbar) taaki CPU→S1 aur DMA→S2 ek saath run ho sakein. Failure 2 — koi QoS/priority nahin. Parallelism ke saath bhi, agar dono same slave ko target karein, toh ek lamba DMA burst time-critical video ko starve kar sakta hai. → demand QoS-aware arbitration taaki arbiter CPU ko preempt/prioritise kar sake. Key insight: yeh orthogonal problems hain. Parallelism "alag destinations collide" fix karta hai; arbitration+QoS "same destination, unequal urgency" fix karta hai. Ek acche fabric ko dono chahiye. Cache Coherence Protocols se compare karo, jo ek teesra, alag problem solve karte hain — duplicated data ko consistent rakhna — jo upar ki kisi bhi feature se cover nahin hota.

Level 4 — Synthesis

Recall Solution

(a) $L + 2$ cycles mein hum $32 L$ bits move karte hain: $Throughput (L) = \frac{32 L}{L + 2} \times 100 \times 1 0^{6} bit/s$ (b) $L = 16$ ke liye: numerator $32 \times 16 = 512$ bits, $16 + 2 = 18$ cycles mein: $\frac{512}{18} \times 100 \times 1 0^{6} \approx 2.844 \times 1 0^{9} bit/s \approx 355.6 MB/s$ (c) 4 bursts in flight ke saath, ek ka overhead doosre ke data ke peeche chhup jaata hai, isliye throughput ~linearly scale karta hai: $\approx 4 \times 355.6 \approx 1422 MB/s \approx 1.42 GB/s$ Overlap kyun kaam karta hai: AXI ke split channels master ko address #2 issue karne dete hain jab data #1 abhi bhi stream ho raha hota hai — fixed 2-cycle tax transactions ke parallel pay hota hai, isliye jab kai outstanding hote hain toh woh matter karna band kar deta hai. Figure s02 dekho: top row ek akela burst dikhata hai jo apne do butter-coloured overhead cells (AR aur R) ko apne data ke ird-gird pay karta hai. Neeche stacked rows mein teen bursts time mein staggered hain — agle burst ka "A" overhead pichle burst ka data abhi bhi stream hote waqt run karta hai, jo exactly wahi reason hai ki yeh tax gayab ho jaata hai. AXI ka AHB par beat karna isi wajah se hai similar per-burst numbers ke bawajood.

Figure s02 — time left to right run karta hai; fixed overhead ko overlap karna hi effective throughput ko single-burst figure ke 4× ke kareeb le jaata hai.

Recall Solution

Single shared bus (APB-style) choose karo. Switch count: $N = 1$ master, $M = 3$ slaves ke liye ek crossbar ko $1 \times 3 = 3$ switches, $3$ arbiters, $3$ comparators chahiye — lekin sirf ek master ke saath kabhi bhi contention nahin hogi, isliye parallelism kuch nahin khareedti. Extra switches pure waste hain. Power angle: har crosspoint switch, arbiter aur comparator aisi logic hai jo static power leak karti hai aur dynamically toggle karti hai. Ek low-power node ke liye tum saari woh logic strip kar dete ho jo koi benefit nahin kama rahi. Ek single shared bus minimal-gate hai → minimal leakage → longest battery life. Rule of thumb: crossbars tabhi pay off karte hain jab multiple masters ek saath alag slaves chahte hain. Ek master ⇒ exploit karne ke liye koi parallelism nahin ⇒ shared bus.

Level 5 — Mastery

Recall Solution

(a) Flat crossbar: $N = 8$ , $M = 16$ . $Switches = 8 \times 16 = 128, Arbiters = 16, Comparators = 16$ (b) Hierarchical. Fast crossbar 4 masters aur (4 fast slaves + 1 APB-bridge port) $= 5$ slave ports dekhta hai: $Fast-crossbar switches = 4 \times 5 = 20$ Us single port ke peeche APB bridge 12 slow slaves ko ek shared bus par fan out karta hai — 0 extra crosspoint switches (shared bus, crossbar nahin). $Total crosspoint switches = 20 + 0 = 20$ Yeh 128 → 20 ki drop hai, crosspoint switches mein roughly 6.4× reduction. (c) Trade-off: humne slow slaves ka parallel access (ab ek APB bridge ke peeche serialised) trade kiya ek massive switch/area/power cut ke liye — yeh exactly isliye acceptable hai kyunki slow peripherals ko rarely concurrent high-bandwidth access ki zaroorat hoti hai. Figure s03 dekho: chaar lavender masters ek single AXI crossbar block ko feed karte hain; uski right side par, chaar mint fast-slaves ko direct crossbar port milta hai, jabki coral APB bridge ek port hai jo 12 grey slow slaves ko ek shared bus par fan out karta hai (koi crosspoints nahin). Caption arithmetic 4×5 = 20 versus flat 8×16 = 128 dikhata hai.

Figure s03 — bahut saare slow slaves ko ek bridge port ke peeche collapse karna hierarchical (Network-on-Chip-style) fabrics ki core trick hai.

Recall Solution

Galat. Burst mode first-word latency nahin reduce karta. Address phase (AW/AR handshake) abhi bhi complete hona chahiye kisi bhi data ke aane se pehle, isliye pehle word ka time same rehta hai chahe burst length 1 ho ya 16. Burst actually kya improve karta hai: throughput (transfer par average bytes per second). $L$ data beats ke liye ek address bhejkar, yeh fixed address/response overhead ko kai words mein amortise karta hai — isliye per word ka average cost girta hai, chahe pehle word ki latency fixed rahe. Master principle: latency = "pehle byte ka time"; throughput = "steady state par bytes per second". Bursts aur pipelining throughput tools hain; yeh initial handshake latency ko waise hi chhhod dete hain. Dono ko confuse karna fabric-analysis mein sabse common error hai.

Recall Quick self-check (clozes)

Woh block jo transaction shuru karta hai woh ek master hai; jo jawab deta hai woh ek slave hai. $N$ masters, $M$ slaves ke liye full-crossbar switch count ::: $N \times M$ Full crossbar mein arbiters ki sankhya ::: $M$ (ek per slave) Kaun sa AXI channel write acknowledgement carry karta hai, aur kis direction mein ::: B (Write Response) channel, slave → master Burst mode throughput improve karta hai, aur first-word latency unchanged rehti hai. APB non-pipelined hai aur per transfer 2 cycles cost karta hai. AXI, AHB aur APB sab kis ARM family se belong karte hain ::: AMBA (Advanced Microcontroller Bus Architecture)