6.3.10 · D1IP cores and SoC bus fabric
Ek SoC ek chhoti city hai jahan pre-built factories (IP cores) ek dusre ko parcels bhejte hain ek shared road system (bus fabric) ke zariye. Is topic mein sab kuch isi ke baare mein hai — kaun parcel bhej sakta hai, kis address pe, aur kitni roads hain taaki kisi ko wait na karna pade.
Yeh page assume karta hai ki aapne kuch nahi dekha. Jab tak aap parent note mein koi AXI channel ya crossbar formula nahi dekhte, aapko har ek word aur symbol pehle se pata hona chahiye. Hum inhe ek ek karke build karte hain, har ek pichle ke upar.
Ek chip silicon ka ek flat tukda hai jisme lakhon tiny switches (transistors) hote hain. Socho ek city jo upar se dikhe : ek bada rectangular plot of land.
Definition Functional blockEk functional block us chip ka ek region hai jo ek kaam karta hai — jaise "arithmetic karo" ya "memory se baat karo". Socho ek building city ke andar.
Agar hum har building se har doosri building tak haath se wire kheechen, toh city sirf ulji hui roads ki jungle ban jaayegi. Woh jungle exactly wahi problem hai jo yeh topic solve karta hai — toh woh picture yaad rakhna.
Left panel dekho: buildings ke beech har pair mein private wires hain — aisa chaos jo tezi se badhta hai. Right panel unhe ek shared road se replace karta hai jisme har building tap karti hai. Woh shared road ek bus ka beej hai.
IP ka matlab hai Intellectual Property . Ek IP core ek functional block hai jo kisine pehle se design karke test kar liya hai, jise aap license lete ho aur apne chip mein drop karte ho — jaise khud har eent lagane ki jagah ek pre-fabricated building kharidna .
Topic ko yeh word kyun chahiye? Kyunki ek SoC ka poora point reuse hai. Aap USB controller scratch se design nahi karte; aap "USB building" kharid ke place karte ho.
Parent note IP cores ko grade karta hai iske hisaab se ki building aate waqt kitni complete hai :
Word
Plain meaning
Picture
Soft IP source text (Verilog/VHDL) ke roop mein aata hai jise aap abhi bhi shape karte hoarchitect ka blueprint — freely reshape karo
Firm IP gate netlist (logic gates ki wiring list) ke roop mein aata haipre-cut lumber — kuch shape fixed
Hard IP fixed physical layout (exact transistor positions) ke roop mein aata hai
finished concrete building — ek wall bhi nahi hila sakte
Intuition Soft → Firm → Hard ek flexibility/performance trade haiBuilding jitni zyada complete aake pahunche, utni fast aur chhoti chalta hai — lekin aap use utna kam change kar sakte ho. Soft = sabse zyada freedom, worst optimisation. Hard = best performance, zero freedom.
Upar ke do words ko aage badhne se pehle apni definition chahiye.
Definition RTL aur Verilog/VHDLRTL (Register Transfer Level) hardware ko describe karne ka ek tarika hai jaise "har clock tick pe, yeh data us storage box mein move karo". Verilog aur VHDL woh do languages hain jinmein log RTL likhte hain. Socho ek recipe jo batata hai har tick pe kya hota hai, abhi tak koi physical object nahi.
Ek netlist ek plain list hai jo kehti hai "gate A ka output wire gate B ke input wire se connect hota hai". Socho ek connect-the-dots sheet : dots (gates) aur kaun si lines unhe join karti hain, lekin abhi zameen pe place nahi kiye.
Definition Gate-level / GDSII / layoutEk gate sabse chhoti logic unit hai (AND, OR, NOT). GDSII woh file format hai jo final physical layout store karta hai — har transistor ki exact shapes aur positions. Socho ek finished street map jisme har building apne plot pe pakki ho.
Har communication ko ek starter aur ek responder chahiye. Hardware do seedhe words use karta hai.
Definition Master aur SlaveEk master woh block hai jo ek transaction start karta hai ("main read/write karna chahta hoon"). Ek slave woh block hai jo sirf tab respond karta hai jab poochha jaaye. Socho ek customer (master) jo ek shop counter (slave) pe jaata hai: customer pehle bolta hai.
Common mistake Ek block dono ho sakta haiEk DMA engine ek slave hai jab CPU usse configure karta hai, phir ek master ban jaata hai jab woh apne aap data move karta hai. "Master/slave" ek role hai ek transaction mein , permanent label nahi.
Ek transaction ek complete request-and-answer hai: ek address jaata hai, data move karta hai, ek acknowledgement wapas aata hai. Socho counter pe poora exchange — poochho, saamaan do, receipt lo.
Parent note teen common master IPs aur unke kaam batata hai — inhe link karo taaki pata chale har building actually kya karta hai:
DMA — ek mover jo CPU ko pareshan kiye bina data le jaata hai.DRAM Controllers — woh building jo main memory chips se baat karta hai.PCIe — chip ke bahar devices se ek high-speed link.
Ek address ek number hai jo ek location ko naam deta hai jahan master pahunchna chahta hai. Socho shared road pe ek street number . Alag alag slaves alag alag number ranges own karte hain.
Definition Address decodingAddress decoding road pe address ko har slave ki number range se compare karna hai yeh decide karne ke liye ki kaun sa slave answer kare . Socho road ka traffic sign: "numbers 0x1000–0x1FFF → RAM ki taraf right lo".
Routing aslmein parcel ko chosen path pe steer karna hai jab decoding ne darwaza choose kar liya. Socho woh junction jo physically RAM ki taraf gate kholti hai.
Yeh idea ki "ek location number hardware ko batata hai kaun sa block respond kare" vault mein apna naam rakhti hai: Memory-Mapped I/O . Har peripheral memory addresses ki ek stretch hone ka natak karta hai.
Figure mein ek address 0x1400 decoder mein enter karta hai. Har slave ek range sign rakhta hai; decoder us ek slave ko light up karta hai jiske range mein 0x1400 aata hai (pink RAM), aur routing sirf woh path kholti hai.
Ek bus wires ka ek shared set hai jisme kai blocks tap karte hain. Socho ek main road . Iska weakness: ek waqt mein sirf ek parcel travel kar sakta hai.
Agar do masters dono ek hi tick pe road chahte hain, toh kisi ko referee karna hoga.
Arbitration woh referee hai jo decide karta hai kaun sa master pehle jaaye jab kaafi saare ek hi resource chahte hain ek saath. Socho junction pe ek traffic cop jo ek car rok ke doosri ko jaane deta hai.
Ab woh key upgrade jiske around poora topic bana hai:
Ek bus fabric ek road network hai, single road nahi: kai parallel paths plus decoders aur arbiters, taaki kai transactions ek saath chalen . Socho ek streets ka grid with traffic cops at each crossing instead of ek shared lane.
Ek crossbar sabse simple full fabric hai: ek physical grid jahan har master ki row har slave ke column se ek crosspoint switch pe connect ho sakti hai. Socho graph paper — rows masters hain, columns slaves hain, aur har intersection ek switch hai jise aap close kar sakte ho.
Figure mein closed switches (yellow dots) gino: master M1, slave S3 tak pahunchta hai jabki M2 independently S1 tak pahunchta hai — do parcels, same instant . Yeh parallelism ek single bus pe impossible hai. Dots ka grid hi wajah hai parent ki formula N × M
Do aur words jo parent freely use karta hai:
Definition N, M, aur × symbolN masters ki sankhya hai, M slaves ki sankhya . Symbol × N × M grid ka area samjho: N M
Worked example Parent ke numbers plug in karoN = 4 M = 8 4 × 8 = 32 8 8 product ki tarah badhta hai, isliye bade SoCs ek flat grid use karna band kar dete hain.
Vault mein in networks ki shapes ke baare mein ek poora page hai: Interconnect Topologies .
O ( ⋅ ) O ( N × M ) N × M rectangle ke area ki tarah badhta hai jo wider aur taller hota jaata hai. Parent ise warn karne ke liye use karta hai ki flat crossbars ~10–20 ports ke baad explode ho jaate hain.
Yeh tool kyun aur plain number kyun nahi? Kyunki hum trend ki parwah karte hain, ek instance ki nahi — Big-O jawab deta hai "kya yeh tab bhi kaam karega jab chip size double ho jaaye?" Ek single number yeh nahi bata sakta; ek growth law bata sakta hai.
Definition Clock aur cycleEk clock ek signal hai jo fixed rate pe on aur off tick karta hai. Ek cycle ek tick hai. MHz (megahertz) millions of ticks per second count karta hai, toh 100 MHz = har second 100 million cycles . Socho ek metronome : har beat data ko ek step move karne ka chance hai.
Definition Bit, byte, aur unke symbolsEk bit ek 0-ya-1 hai. Ek byte 8 bits hai. "32-bit data" matlab 32 wires ek saath data carry karti hain. Socho 32 parallel lanes , har ek har beat pe ek 0/1 carry karti hai.
Throughput hai har second kitna data move karta hai . Iska recipe: bits-per-transfer, cycles-per-transfer se divide karo, times ticks-per-second.
Throughput = cycles per transfer bits per transfer × clock rate
Worked example Parent ka APB number rebuild karoAPB ko 32 bits ke transfer ke liye 2 cycles chahiye 100 MHz pe:
2 cycles 32 bits × 100 000 000 /s = 1.6 × 1 0 9 bit/s = 1.6 Gb/s = 200 MB/s 1.6 Gb/s = 200 MB/s
Pipelining matlab hai agla kaam shuru karna isse pehle ki current wala poora khatam ho, jaise assembly line. Socho ek laundromat : aap load 2 dhona shuru karte ho jab load 1 sukh raha hota hai, instead of wait karne ke.
Ek burst matlab hai ek address bhejo, phir kaafi saare data words back-to-back. Socho postman ko ek street number do aur chaar parcels haath mein do — address chaar baar repeat karne ki zaroorat nahi.
Ek channel ek dedicated set of wires hai ek tarah ki traffic ke liye . AXI kaam ko 5 channels mein split karta hai (write-address, write-data, write-response, read-address, read-data). Socho paanch alag conveyor belts , taaki ek address travel kar sake jabki doosri belt pe data flow karta rahe — parent ka poora "parallelism" argument isi pe based hai.
Recall Address aur data channels alag kyun?Kyunki unki timings alag hoti hain — slave ek address accept kar sakta hai aur prepare kar sakta hai jabki master abhi data gather kar raha hota hai. Alag belts dono ko ek saath hone deti hain instead of ek doosre ko block karne ke.
Definition QoS (Quality of Service)QoS ek priority scheme hai: important traffic (live video) road pehle paata hai unimportant traffic se pehle (background copy). Socho ek ambulance lane — arbiter hamesha ambulance ko pehle jaane deta hai. Related on-chip concern: Power Management aksar yeh arbitration logic share karta hai idle blocks ko slow karne ke liye.
Ek aur prerequisite word jo parent freely use karta hai jab kai masters memory share karte hain:
Definition Coherence (preview)Cache coherence ka matlab hai usi data ki copies ko consistent rakhna jab kai masters usse cache karte hain. Aapko bas yahan itna jaanna hai ki yeh exist karta hai; deep treatment Cache Coherence Protocols mein hai.
chip and functional block
pipelining bursts channels
Right side cover karo aur khud test karo. Agar koi answer fuzzy lage, toh woh section phir padhna.
IP core kya hai, ek line mein? Ek pre-designed, pre-tested functional block jise aap license karte ho aur chip mein drop karte ho — ek pre-fab building.
Soft vs Hard IP — kaun zyada flexible hai, kaun faster? Soft sabse zyada flexible hai (source text jise aap reshape karo); Hard fastest/smallest hai (fixed physical layout).
Pehle kaun bolta hai, master ya slave? Master — woh transaction start karta hai; slave sirf respond karta hai.
Address decoding kya decide karta hai? Kaun sa slave address own karta hai, taaki request sahi darwaaze pe route ho.
Plain bus performance kyun limit karta hai? Ek waqt mein sirf ek transaction ek single shared road use kar sakta hai.
Bus fabric, bus ke upar kya add karta hai? Parallel paths plus decoders aur arbiters, taaki kai transactions simultaneously chalen.
Ek N×M crossbar ko kitne switches chahiye, aur kyun? N × M — har master–slave pair ke liye ek crosspoint switch (grid ka area).
O ( N × M ) Cost N·M ke product ke proportion mein badhti hai, toh flat crossbars SoC scale karne pe explode ho jaate hain.
Throughput formula likhna. (bits per transfer ÷ cycles per transfer) × clock rate.
AXI 5 alag channels kyun use karta hai? Traffic type ke hisaab se dedicated wires address, data, aur response ko parallel mein flow karne deti hain (pipelining).
Burst kya hai? Ek address ke baad kaafi saare data words back-to-back, address overhead amortise karte hue.
Fabric pe QoS kya provide karta hai? Priority arbitration taaki time-critical traffic low-priority traffic se pehle road jeet sake.
