IP cores and SoC bus fabric: Visual walkthrough — Hinglish deep dive

6.3.10 · D2 · Hardware › Interconnects, Buses & SoC › IP cores and SoC bus fabric

Ye page parent ka central result — crossbar complexity formula $switches = N \times M$ — bilkul scratch se rebuild karta hai. Hum do chips se shuru karte hain jo baat karna chahte hain, aur picture ko ek ek wire se badhate hain, jab tak ki $N \times M$ number apne aap saamne na aa jaaye.

Tumhe ye jaanna zaroori nahi ki "bus", "master", ya "arbiter" kya hota hai. Hum har ek ko theek uss waqt define karte hain jab zaroorat padti hai, aur draw karte hain.

Step 1 — Do blocks, ek wire: "baat karna" ka matlab kya hai

KYA. Ek master (usse $M_{1}$ kaho) ko left mein rakho aur ek slave ( $S_{1}$ ) ko right mein. Dono ke beech ek line khicho.

KYUN. Bahut saare wires count karne se pehle, humein agree karna hoga ki ek connection kya hota hai. Connection koi bhi physical path hai jiske through ek request master se slave tak flow kar sake. Ek master, ek slave → exactly ek path chahiye.

PICTURE. Blue box master hai, green box slave hai, yellow line woh ek path hai jo $M_{1}$ ko $S_{1}$ tak pahunchne deta hai.

paths = masters 1 \times slaves 1 = 1

Pehla $1$ count karta hai ki kitne blocks conversation shuru kar sakte hain.
Doosra $1$ count karta hai ki kitne blocks jawab de sakte hain.
Unka product count karta hai master–slave pairs ko jo kabhi bhi mile ho sakte hain — yahan sirf ek.

Woh word pair yaad rakho. Poora formula actually pairs ka count hai.

Step 2 — Doosra slave add karo: ek master, do destinations

KYA. $M_{1}$ rakho. Ek doosra slave $S_{2}$ add karo (maano UART, jabki $S_{1}$ RAM hai). Ab $M_{1}$ kisi bhi ek ko chahta ho sakta hai.

KYUN. Ek real CPU kai cheezein se baat karta hai: memory, timer, serial port. Har ek alag address par alag slave hai. Agar $M_{1}$ ko dono tak pahunchna hai, toh usse har ek ka path chahiye.

PICTURE. Do yellow lines $M_{1}$ se nikalti hain — ek $S_{1}$ ko, ek $S_{2}$ ko. Woh chota diamond jahan ek line ek slave se milti hai woh ek switch hai: ek gate jo ya toh open hai (yeh path current transaction carry kar raha hai) ya closed.

paths from M_{1} = M_{1} 1 \times S_{1}, S_{2} 2 = 2

$1$ = woh single master jo pooch raha hai.
$2$ = doors ( $S_{1}$ , $S_{2}$ ) ki number jinhe woh knock kar sakta hai.
Product $= 2$ switches, kyunki har door ka apna gate chahiye.

Step 3 — Doosra master add karo: ab paths ek saath ho sakti hain

KYA. Master $M_{2}$ add karo (ek DMA engine — ek block jo CPU ke bina memory copy karta hai, dekho DMA). Usse apni do lines do, har slave ko ek.

KYUN — key idea. Ek simple bus mein ek waqt mein sirf ek master bol sakta hai; agar CPU wire use kar raha hai, DMA wait karta hai. Ek crossbar iska baar baar har master ko uski apni set of wires deta hai taaki do conversations concurrently chal sakein — $M_{1} \to S_{1}$ jabki $M_{2} \to S_{2}$ . Woh parallelism hi poori wajah hai ki hum extra switches kharchte hain.

PICTURE. Left mein do blue masters, right mein do green slaves. Har master ki har slave tak ek line hai. Diamonds count karo: chaar hain.

switches = N = masters 2 \times M = slaves 2 = 4

$N$ = masters ki number (grid mein rows).
$M$ = slaves ki number (grid mein columns).
Multiply kyun? Har ek $N$ masters ke liye hum $M$ switches lagate hain (Step 2 ne $M$ switches per master diye). Ye $N$ baar karne se $N$ identical rows stack hoti hain → $N \times M$ total. Multiplication bas " $N$ copies of $M$ " hai.

Step 4 — Collision problem: do masters, ek slave

KYA. Dono $M_{1}$ aur $M_{2}$ ek hi clock cycle mein $S_{1}$ chahte hain.

KYUN. $S_{1}$ mein do switches ek saath open hain → do masters ek hi waqt $S_{1}$ ke single input par data dhakelte hain. Yeh ek electrical fight hai; data garbage hota hai. Humein ek referee chahiye.

PICTURE. Dono masters $S_{1}$ pe aim kar rahe hain (red = conflict). Ek red arbiter block $S_{1}$ ke darwaze par baitha hai aur exactly ek ko andar jaane deta hai; doosre ki request rok li jaati hai.

Kitne arbiters? Collision sirf ek slave par ho sakta hai (wahan paths milti hain). Toh humein har slave ke liye ek arbiter chahiye:

arbiters = one per slave M

Yahi reasoning address comparators ko naam deti hai: har slave ke paas addresses ki ek range hoti hai, aur kuch check karna chahiye "kya is request ka address mera hai?" — ek comparator per slave, woh bhi $M$ .

Step 5 — General grid: teeno counts padhna

KYA. General $N$ masters aur $M$ slaves ke saath redraw karo. Rows ko $M_{1} \dots M_{N}$ aur columns ko $S_{1} \dots S_{M}$ label karo.

KYUN. Steps 1–4 ne har piece ko chote examples par banaya. Ab hum bas grid padhte hain aur parent ka formula kisi bhi size ke liye lete hain.

PICTURE. Ek poora $N \times M$ lattice. Har crossing ek switch hai (blue). Har column ke neeche ek arbiter + ek address comparator hai (red).

Step 6 — Ye kaam karna band kyun karta hai: $N \times M$ growth curve

KYA. Switch count ko plot karo jaise $N$ aur $M$ saath badhte hain (maano $N = M = n$ , toh switches $= n^{2}$ ).

KYUN. Parent kehta hai flat crossbars "~10–20 ports se aage scale nahi hote." Yahan ek picture mein reason hai: ports double karne se switches chaar guna ho jaate hain. Cost area ki tarah badhti hai, length ki tarah nahi.

PICTURE. Blue curve $n^{2}$ (crossbar) yellow line $n$ (ek single shared bus) ko rocket ki tarah paar kar jaati hai. $n = 20$ par woh $400$ switches chip par hain — woh point jahan designers hierarchical topology ya Network-on-Chip par switch karte hain.

switches (n) = n \times n = n^{2} ⟹ switches (2 n) = (2 n)^{2} = 4 n^{2}

$n^{2}$ square grid par count hai.
$n$ ko $2 n$ se replace karne par $4 n^{2}$ milta hai: chaar guna switches do guna ports ke liye. Woh quadratic blow-up hi woh wall hai.

Step 7 — Degenerate cases: corners check karo

Har honest derivation ko apni extremes mein survive karna chahiye. Formula ko tiny/empty inputs do.

Case	$N$	$M$	switches $= N \times M$	Kya picture agree karti hai?
Koi baat nahi karta	$0$	koi bhi	$0$	Koi masters nahi → koi wires nahi. ✔
Baat karne ko kuch nahi	koi bhi	$0$	$0$	Koi slaves nahi → koi destinations nahi. ✔
One-to-one link	$1$	$1$	$1$	Exactly Step 1 ka single wire. ✔
Single shared bus	$N$	$M$ but 1 path	(bus 1 wire share karta hai, $N M$ nahi)	Sasta, lekin ek waqt mein sirf 1 transaction — Step 3 ka parallelism gone.

Formula gracefully degrade karta hai: kisi bhi factor ko $0$ set karo aur correctly $0$ switches milte hain — koi special-casing required nahi.

Ek-picture summary

Ek master–slave pair (Step 1) → ek master ke liye $M$ switches ki ek row (Step 2) → $N$ aisi rows stack karo $N \times M$ switches ke poore grid ke liye (Step 3) → har $M$ columns ke neeche ek arbiter lagao collisions settle karne ke liye (Step 4) → saare costs padho (Step 5) → aur count ko $n^{2}$ ki tarah explode hote dekho taaki pata chale kab rukna hai (Step 6).

Recall Feynman retelling — plain words mein wapas kaho

Left mein blocks imagine karo jo poochte hain aur right mein blocks jo jawab dete hain. Agar ek poochne wale ko kai jawab dene waalon tak pahunchna ho, toh usse har jawab dene waale ke liye ek chota on/off gate — ek switch — chahiye. Saare poochne waalon ko rows mein aur saare jawab dene waalon ko columns mein rakho; jahan bhi ek row ek column cross karti hai wahan ek switch daalo. Toh switches ki number bas rows times columns hai: $N$ times $M$ . Jab do poochne waale ek hi jawab dene waale ko pakad lete hain, toh collide karte hain, toh har jawab dene wala ek referee (arbiter) apne darwaze par rakhta hai — ek referee per column, yani $M$ total. Poori cheez ek rectangle hai: rows $\times$ columns squares. Isliye cost rectangle ke area ki tarah badhti hai, aur isliye sab kuch double karne se switches chaar guna ho jaate hain — yahi woh waqt hai jab engineers flat grid chhod ke kuch smarter banate hain.

Recall

$N$ masters aur $M$ slaves ke full crossbar ko kitne switches chahiye? ::: $N \times M$ — ek per (master, slave) pair. Per master nahi, per slave ek arbiter kyun? ::: Collisions wahan hoti hain jahan paths milti hain — ek slave par — toh har slave (column) ko apna referee chahiye, yani $M$ arbiters milte hain. Extra $N \times M$ switches ek single shared bus ke upar kya khareedti hain? ::: Concurrency — $M_{1} \to S_{1}$ ek saath chal sakti hai jab $M_{2} \to S_{2}$ chal rahi ho. Agar tum $N$ aur $M$ dono double kar do, toh switch count kaise change hota hai? ::: Chaar guna ho jaata hai, kyunki $(2 n)^{2} = 4 n^{2}$ .

Related: Interconnect Topologies · Cache Coherence Protocols · Memory-Mapped I/O · DMA · PCIe