Worked examples — System-on-Chip (SoC) integration

6.3.9 · D3 · Hardware › Interconnects, Buses & SoC › System-on-Chip (SoC) integration

Yeh page parent topic ka drill hall hai. Parent ne tumhe bataya tha ki pieces kya hain (IP blocks, interconnect, CDC, power domains). Yahan hum har tarah ke scenario tumhare saamne rakhte hain aur har ek ko number tak solve karte hain, taaki exam mein ya real design review mein koi aisa case na aaye jo tumne pehle dekha na ho.

Koi bhi formula aane se pehle, yaad karo ki is topic mein char number-producing tools hain. Har ek ko hum tab dobara earn karenge jab woh aayega. Har symbol us moment define kiya jayega jab woh pehli baar aata hai:

• Crossbar bandwidth $B_{\text{total}}=\min (M,N)\times B$ — jahan $M$ = masters ki sankhya (jo cheezein requests issue karti hain, jaise CPU), $N$ = slaves ki sankhya (jo cheezein jawab deti hain, jaise memory), $B$ = ek link ki bandwidth GB/s mein. Jawab deta hai "ek waqt mein kitne transfers ho sakte hain?"
• Metastability MTBF $\text{MTBF}\propto e^{T_{\text{wait}}/\tau }$ — jahan $T_{\text{wait}}$ = woh time jo hum ek flop ko settle hone dete hain, $\tau$ = transistor ka settling time-constant. Jawab deta hai "agar main $T_{\text{wait}}$ wait karun toh crashes ke beech kitna time hoga?"
• Dynamic power $P_{\text{dyn}}=\alpha C{V}^{2}f$ — jahan $\alpha$ (activity factor) = un clock cycles ka fraction jisme koi node actually switch karta hai (0 aur 1 ke beech ek pure number; agar ek wire har doosre cycle mein toggle kare toh $\alpha =0.5$), $C$ (capacitance) = charge hone wali saari wires ka electrical "bucket size", farads mein (bade nodes zyada charge store karte hain), $V$ = supply voltage, $f$ = clock frequency. Jawab deta hai "switching mein per second kitni energy jalti hai?"
• Address decode address[31:12] == base — is notation ki poori derivation Example 7 mein fresh ki gayi hai (tab tak shorthand par trust mat karo). Abhi loosely padho: "kya is request ke high bits kisi peripheral ke start tag se match karte hain?" Jawab deta hai "is request ka owner kaun sa slave hai?"

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The scenario matrix

Har SoC-integration question is grid ka ek cell hai. Neeche ke worked examples un cell(s) ke saath tagged hain jo woh cover karte hain, taaki end mein har cell filled ho.

Cell	Case class	Tricky kyu hai	Covered by
A	Crossbar — best case ($M\le N$, sab distinct)	max parallelism	Ex 1
B	Crossbar — worst case (sab ek hi slave ko target karte hain)	serialization	Ex 1
C	Crossbar — degenerate ($N=1$, single memory)	$\min (M,1)=1$	Ex 2
D	Crossbar — $M>N$ (masters zyada, slaves kam)	slave side ke ports limit karte hain	Ex 2
E	CDC — single bit, MTBF sizing	wait time mein exponential	Ex 3
F	CDC — multi-bit bus, tiny-but-nonzero failure	2-flop fail karta hai, tool badalna padega	Ex 4
G	Power — steady power-gating savings + overhead	duty cycle weighting, break-even	Ex 5
H	Power — voltage scaling (DVFS), $V^2$ law	$V$ mein quadratic	Ex 6
I	Address map — no overlap / decode	half-open ranges, off-by-one traps	Ex 7
J	Word problem (real phone SoC)	sahi tool chunna	Ex 8
K	Exam twist (do tools combine karo)	interconnect aur power saath	Ex 9
L	Limiting behaviour ($T_{\text{wait}}\to 0$, $V\to 0$)	edge sanity checks	Ex 10

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Example 1 — Crossbar best case vs worst case (cells A, B)

Forecast: padhne se pehle guess karo. Best case mein "kai links ek saath" hona chahiye; worst case mein "sirf ek link". Apne do numbers likh lo.

Figure caption — the crossbar grid. Har row ek master hai (CPU, GPU, DMA, DSP), har column ek slave hai (S0…S5). (row $i$, column $j$) par cell master $i$ se slave $j$ tak ka possible path hai. Ek lit amber cell is cycle mein ek active transfer hai. Jo rule picture enforce karti hai: crossbar zyada se zyada ek cell per row (master ek cheez issue karta hai) aur ek cell per column (slave ek hi master ko jawab deta hai) light kar sakta hai. Jo chaar amber cells drawn hain woh alag-alag rows aur alag-alag columns mein hain — yahi best case hai, aur unhe count karne se tum part (a) ka jawab seedha paa sakte ho. Ab steps:

1. Count karo ki ek saath kitne cells lit ho sakte hain. "One-per-row and one-per-column" rule use karke, jo figure mein dikhta hai, simultaneously lit cells ki maximum sankhya #rows aur #columns mein se chhota hai. Yeh step kyu? Isliye yeh tool $\min (M,N)$ hai, $M+N$ ya $M\times N$ nahi — ek slave jiske paas single port (ek column) hai woh ek hi cycle mein do masters ko jawab nahi de sakta, toh lit cells kabhi columns ki sankhya se zyada nahi ho sakte, aur na hi rows ki sankhya se.
2. Best case ke liye plug in karo. $\min (M,N)=\min (4,6)=4$. Toh $B_{\text{total}}=4\times 8=32$ GB/s. Yeh step kyu? $M\le N$ ka matlab hai har master apna khud ka distinct slave (apna column) dhundh sakta hai → charon parallel mein transfer karte hain, exactly figure mein chaar amber cells.
3. Worst case: sab slave 0 ko target karte hain. Ab sirf column 0 lit ho sakta hai, aur us mein sirf ek cell. Toh ek transfer: $B_{\text{total}}=1\times 8=8$ GB/s. Yeh step kyu? Arbitration charon requests ko slave 0 ke single port (single column) se serialize kar deti hai.

Verify: Best case $32$ GB/s = single-link $8$ GB/s ka $4\times$ — "4 parallel lanes" = 4 lit cells se match karta hai. Worst case $8$ = ek link — "sab queue mein" = ek lit cell se match karta hai. Units: (links)$\times$(GB/s) = GB/s. ✓

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Example 2 — Single memory & more masters than slaves (cells C, D)

Forecast: (a) ek degenerate case hai — aath logon ke liye ek darwaza. (b) mein darwazon se zyada masters hain.

Figure caption — do collapsed grids. Left grid: $8$ rows (masters) lekin sirf ek column, toh zyada se zyada ek amber cell lights — crossbar ek shared bus ban gaya. Right grid: $8$ rows, $3$ columns, teen amber cells distinct columns mein — slave side (3 columns) cap lagata hai kitne light ho sakte hain, chahe kitni bhi rows hon. Picture $\min (M,N)$ ko obvious bana deti hai: jab columns zyada kam hon toh columns count karo.

1. (a) $\min (M,N)$ apply karo. $\min (8,1)=1$, toh $B_{\text{total}}=1\times 6=6$ GB/s. Yeh step kyu? Ek slave = ek port = ek transfer per cycle, chahe kitne bhi masters hon. Baaki 7 masters bas wait karte hain — crossbar ek shared bus mein collapse ho jaata hai (left grid).
2. (b) Slave side bottleneck hai. $\min (8,3)=3$, toh $B_{\text{total}}=3\times 6=18$ GB/s. Yeh step kyu? 8 eager masters ke bawajood, sirf 3 slaves ek saath answer kar sakte hain. Jab $M>N$ hota hai, answer $N$ se cap hota hai — master count $N$ se upar matter karna band ho jaata hai (right grid, 3 lit columns).

Verify: (a) mein masters add karne se bandwidth $6$ se aage kabhi nahi badhti — sanity: ek memory apne port se zyada nahi de sakta. (b) mein $18=3\times 6$ aur $3=N<M$ toh cap slave side par hai. ✓

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Example 3 — CDC single-bit synchronizer MTBF (cell E)

Pehle humein MTBF tool earn karna hoga. Jab synchronizer ka pehla flop ek changing signal sample karta hai, uska output half-voltage ("metastable") par hang ho sakta hai, thodi der ke liye, 0 ya 1 par snap karne se pehle. Probability ki woh $T_{\text{wait}}$ wait karne ke baad abhi bhi undecided hai, woh $e^{-T_{\text{wait}}/\tau }$ ki tarah shrink hoti hai, jahan $\tau$ (~$0.1$ ns) hai woh speed jis par transistor "apna man banata hai". Kyunki failures exponentially rare hote jaate hain, mean time between failures hai

$\text{MTBF}=\frac{e^{T_{\text{wait}}/\tau }}{T_0{f}_{\text{clk}}{f}_{\text{data}}}$

Do device constants physically kya hain? Ek metastable flop ek hill par balance ball ki tarah behave karta hai: center se jitna door shuru ho, utni jaldi roll off karta hai. $\tau$ (resolution time-constant, units: seconds, ~$0.1$ ns) hai kitni jaldi woh roll karta hai — transistor ke gain aur load ki property, toh bade/tez transistors $\tau$ chota dete hain aur jaldi settle karte hain. $T_0$ (metastability window constant, units: seconds, ~$1$ ns) measure karta hai ki clock edge ke around "danger window" kitna wide hai — un input arrival times ka sliver jo bilkul metastable event trigger kar sakta hai. Yeh flop ke aperture (setup+hold region) se aata hai aur given cell ke liye bench par measure hota hai. Denominator $T_0{f}_{\text{clk}}{f}_{\text{data}}$ saath milke per second metastable events attempted count karta hai: window kitna wide hai ($T_0$) $\times$ hum kitni baar sample karte hain ($f_{\text{clk}}$) $\times$ data us window mein kitni baar toggle karta hai ($f_{\text{data}}$). Exponential numerator phir batata hai ki un attempts mein se kitne wait survive karte hain. Hum exponential use karte hain, linear model nahi, kyunki settling ek decay process hai — jitna deep wait karo, utna disproportionately safer hota jaata hai.

Figure caption — the resolution decay. Amber curve hai $e^{-T_{\text{wait}}/\tau }$: probability ki ek flop $T_{\text{wait}}$ wait karne ke baad abhi bhi undecided hai. Yeh cliff se girta hai. Vertical cyan lines $T_{\text{wait}}=2$ ns (2-flop) aur $4$ ns (3-flop) mark karti hain — dekho ki doosra flop tumhe tail mein kitna door push karta hai.

Forecast: $T_{\text{wait}}/\tau =2/0.1=20$, aur $e^{20}$ enormous hai, toh expect karo saal, seconds nahi.

1. Exponent compute karo. $T_{\text{wait}}/\tau =2\text{ ns}/0.1\text{ ns}=20$, aur $e^{20}\approx 4.85\times 10^8$. Yeh step kyu? Yahi factor doosra flop add karne ka poora payoff hai.
2. Denominator compute karo (failures/second scale). $T_0{f}_{\text{clk}}{f}_{\text{data}}=(10^{-9})(5\times 10^8)(10^7)=5\times 10^6$ s${}^{-1}$. Yeh step kyu? Yeh hai kitni baar ek metastable event attempt hota hai — zyada clocking aur zyada toggling = fail hone ke zyada chances.
3. Divide karo. $\text{MTBF}=\frac{4.85\times 10^8}{5\times 10^6}\approx 97$ s. Yeh step kyu? Actual mean time yield karta hai — yahan woh bahut chhota hai, jo batata hai ki 2 flops kaafi nahi hain in rates par.

Verify: $97$ s embarrassingly short hai — acha hai, yeh demonstrate karta hai kyu fast/heavily-toggling signals ko teesra flop chahiye (aur $2$ ns add karo): exponent $40$ ho jaata hai, $e^{40}\approx 2.35\times 10^{17}$, MTBF $\approx 4.7\times 10^{10}$ s $\approx$ 1500 saal. Exponential wait decisively jeetta hai. ✓

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Example 4 — Multi-bit bus: 2-flop failure probability (cell F)

Forecast: lagta hai "mostly work" karega. Chalte hain failure par number lagaate hain.

1. Ek bit ke skew probability ka model banao. 32 bits mein se har ek independently synchronize karta hai. Jab kai bits ek hi source cycle par change hoti hain, koi ek bit ek destination cycle late resolve ho sakti hai agar woh metastable ho gayi thi aur slowly settle hui. Maano $p$ probability hai ki koi transitioning bit ek cycle late resolve kare; Example 3 ki same physics se, $p\approx e^{-T_{\text{wait}}/\tau }$ per event — chhota, lekin strictly greater than zero. Yeh step kyu? Hum vague "it might break" ko ek real per-bit probability se replace karte hain taaki 32 bits add kar sakein.
2. Bus ke across combine karo. Word galat capture hota hai agar 32 bits mein se koi ek bhi skewed ho. Saath toggle hoti $k$ bits ke saath, probability ki poora word cleanly capture ho $(1-p{)}^k$ hai, toh $P_{\text{corrupt}}=1-(1-p{)}^k\approx kp(\text{for small }p).$ Yeh step kyu? Independent bits multiply hote hain; failure probability roughly linearly bits ki sankhya ke saath badhti hai. Yeh tiny but not zero hai — aur yeh har multi-bit change par dobara hoti hai, toh billions of transfers mein corruption inevitable hai. (Yahi correction hai: "absolute zero probability" nahi, balki "small $p$ per bit, $\approx kp$ per word, time ke saath certain failure tak accumulate hona".)
3. Tool switch karo taaki $k$ effectively 1 ho jaaye. Ek handshake use karo (32 bits ko static rakhho, sirf ek 1-bit valid synchronize karo) ya ek async FIFO Gray-coded pointers ke saath taaki sirf ek pointer bit per step change ho. Yeh Gray code kyu? Kyunki single-bit change $k=1$ bana deta hai, $P_{\text{corrupt}}\approx kp$ ko wapas single-bit MTBF par collapse karta hai jise humne Example 3 mein already safely size kiya tha.

Verify: $p$ chhote aur $k=32$ ke saath, $P_{\text{corrupt}}\approx 32p$ — ek bit se baatees guna bura, aur kabhi exactly zero nahi. $k=1$ par reduce karna Example 3 ki reliability wapas laata hai. Consistency: 1 bit ⇒ Example 3 apply; 32 bits ⇒ control ko 1 bit par reduce karna hoga. ✓ Async bridge ke liye Clock Domain Crossing Techniques aur AXI Protocol dekho jo yeh karta hai.

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Example 5 — Power-gating savings aur uska break-even (cell G)

Forecast: (a) ≈ "leakage times off-fraction". (b) overhead per event chhota hai lekin gating ki frequency se multiply hota hai.

1. (a) Baseline (idle-powered) average. $0.15\times 1.5+0.85\times 0.4=0.225+0.34=0.565$ W. Yeh step kyu? Har state ko uske time fraction se weight karo — yahi "average power" ka matlab hai.
2. (a) Ideal power-gated average. Active abhi bhi $0.15\times 1.5=0.225$ W; off state $\approx 0$ draw karta hai: total $=0.225$ W. Naive savings $=0.565-0.225=0.34$ W. Yeh step kyu? Power-gating off window mein dynamic aur static dono power remove karta hai; removed part exactly leakage ka $0.85\times 0.4=0.34$ W hai.
3. (b) Transition penalty add karo. $n=200$ times/s wake hone par $E_{\text{wake}}=0.5$ mJ ka cost $P_{\text{overhead}}=n\times E_{\text{wake}}=200\times 0.5\times 10^{-3}=0.1$ W hai. Yeh step kyu? Har on/off cycle domain ki capacitance recharge karta hai — woh energy, jitni baar karo, ek continuous power cost hai jo $0.34$ W saved mein se khaata hai.
4. (b) Net savings. $0.34-0.1=0.24$ W abhi bhi saved. Break-even wahan hai jahan $n\times E_{\text{wake}}=0.34$ W, yani $n_{\text{max}}=0.34/0.5\text{e-}3=680$ gate cycles/s. Us se upar, gating loss karti hai. Yeh step kyu? Parent note ki warning quantify karta hai: power-gating tabhi faydaymand hai jab block itni der off rahe ki leakage saved > wake-up energy. $t_{\text{wake}}=50\mu$s latency ka matlab yeh bhi hai ki tum kisi block ko gate mat karo jo $\sim$tens of $\mu$s mein phir chahiye ho.

Verify: Overhead $=200\times 0.5\text{ mJ}=0.1$ W; net $=0.34-0.1=0.24$ W $>0$ ⇒ yahan worth it hai. Break-even $n=0.34/0.0005=680$/s; hamara $200<680$ ✓. Units: (events/s)$\times$(J) = W. ✓ Power Management in SoCs dekho.

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Example 6 — DVFS aur $V^2$ law (cell H)

Yahan tool hai $P_{\text{dyn}}=\alpha C{V}^{2}f$. Hum $V^2$ use karte hain, $V$ nahi, kyunki har switching node ek capacitor $C$ ko voltage $V$ tak charge karta hai, energy $\frac{1}{2}C{V}^2$ store karta hai — energy square ke saath scale karta hai. Isliye voltage kam karna sabse powerful knob hai.

Forecast: dono $V^2$ (0.64$\times$) aur $f$ (0.6$\times$) drop hote hain — expect karo roughly ek-teesra original.

Figure caption — do bars. Lamba amber bar hai $P_1\propto V_1^2{f}_1=2.0$ (arbitrary units); chota cyan bar hai $P_2\propto V_2^2{f}_2=0.768$. Jo gap tum dekh sakte ho woh $61.6\%$ removed hai. Note karo ki voltage contribution ($0.64$) frequency contribution ($0.6$) se zyada kaam karta hai — square zyada kaat ta hai.

1. Ratio banao taaki $\alpha ,C$ cancel ho jaayein. $\frac{P_2}{P_1}=\frac{V_2^2{f}_2}{V_1^2{f}_1}=\frac{(0.8{)}^2(1.2)}{(1.0{)}^2(2.0)}.$ Yeh step kyu? Fractional answer ke liye sirf changing quantities matter karti hain; constant activity factor $\alpha$ aur capacitance $C$ top aur bottom cancel ho jaate hain.
2. Compute karo. $(0.8{)}^2=0.64$; $0.64\times 1.2=0.768$; $0.768/2.0=0.384$. Yeh step kyu? Voltage-square factor ko frequency factor se multiply karo.
3. Interpret karo. $P_2/P_1=0.384$, toh power $38.4\%$ tak girti hai — ek $61.6\%$ reduction. Yeh step kyu? Ek ratio tab tak meaningless hai jab tak hum use "kitna save hua?" mein translate na karein; $1-0.384=0.616$ power ka woh fraction hai jo remove hua, yahi woh number hai jo ek engineer DVFS state justify karne ke liye report karta hai.

Verify: Reduction $=1-0.384=0.616$. Do knobs alag-alag cross-check karo: voltage alone $0.64$, frequency alone $0.6$; product $0.384$. ✓ Isliye phones voltage aur clock saath mein kaatte hain.

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Example 7 — Address map: half-open ranges aur decode (cell I)

Kisi bhi hex se pehle, humein decode notation scratch se dobara earn karni hogi, kyunki summary ne sirf sketch kiya tha.

Forecast: 4 KB $=0x1000$ bytes, toh agla block ...0FFF ke ek baad start hota hai.

1. Interval convention choose karo. Har window ko half-open interval $[\text{start},\text{start}+\text{size})$ ki tarah describe karte hain — start inclusive, end exclusive. Toh 0x4000_0000 par 4 KB block hai $[0x4000\_0000,0x4000\_1000)$, matlab uska last valid byte 0x4000_0FFF hai. Yeh step kyu? Half-open intervals off-by-one bugs khatam karte hain: agla block exactly pichle block ki end value par start hota hai, koi overlap nahi aur koi gap-of-one nahi. Inclusive/inclusive har jagah awkward $-1$ force karega.
2. Size hex mein. 4 KB $=2^{12}=0x1000$; 64 KB $=2^{16}=0x1\_0000$. Yeh step kyu? Sizes powers of two honi chahiye taaki step 5 ka bit-slice decode ek clean prefix compare ho.
3. Do 4 KB blocks lay out karo. UART: $[0x4000\_0000,0x4000\_1000)$ → last byte 0x4000_0FFF. GPIO pichli end value se start hota hai: $[0x4000\_1000,0x4000\_2000)$ → last byte 0x4000_1FFF. Yeh step kyu? Har start = pichla half-open end; dono starts 4 KB-aligned hain (low 12 bits zero), toh cleanly decode hote hain.
4. 64 KB DMA block natural-alignment rule ke saath place karo. Size $S$ ka block $S$ ke multiple par start hona chahiye taaki uske start aur end same high bits share karein (ek prefix compare use select karti hai). DMA ke liye, $S=0x1\_0000$, toh base mod 0x10000 == 0. GPIO ke baad next free byte 0x4000_2000 hai, lekin $0x4000\_2000\mathrm{mod}0x1\_0000=0x2000\ne 0$ — aligned nahi. Next multiple tak round up karo: 0x4001_0000 (kyunki $0x40010000\mathrm{mod}0x10000=0$). DMA occupies $[0x4001\_0000,0x4002\_0000)$ → last byte 0x4001_FFFF. Yeh step kyu? DMA ko 0x4000_2000 par rakhne se uska 64 KB span $0x1\_0000$ boundary cross karega, toh ek single prefix compare use isolate nahi kar sakta. Rounding ek intentional unused gap 0x4000_2000–0x4000_FFFF create karta hai — normal aur sasta hai.
5. UART decode karo. UART ko route karo iff address[31:12] == 0x40000. Yeh step kyu? Low 12 bits (in-window offset) drop karne se unique 20-bit page tag milta hai = UART base.
6. Boundary tests (half-open in action). 0x4000_0FFF >> 12 = 0x40000 → UART ✓ (yeh UART ke half-open interval ka last byte hai). 0x4000_1000 >> 12 = 0x40001 → UART nahi; yeh GPIO ka start hai (GPIO mein included, UART se excluded). Yeh step kyu? Yahi classic off-by-one hai: boundary address 0x4000_1000 GPIO ka hai precisely kyunki UART ka interval half-open hai aur apna khud ka end exclude karta hai.

Verify: UART span $=0x1000=4096$ bytes ✓. Koi overlap nahi, koi gap-of-one nahi: UART end value 0x4000_1000 = GPIO start ✓. DMA base 0x40010000 0x10000 ka multiple hai (aligned) ✓ aur uska half-open interval $[0x40010000,0x40020000)$ GPIO ke end 0x40002000 ko touch nahi karta. Routing: 0x40000FFF>>12=0x40000 (UART) lekin 0x40001000>>12=0x40001 (GPIO) — differ karte hain ✓. ✓

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Example 8 — Real phone SoC word problem (cell J)

Forecast: blindly $\min (6,4)$ mat use karo — active count padho.

Figure caption — teen competing caps. Teen cyan bars: masters present ($6$), memory ports ($4$), masters active ($4$). Ek amber line sabse chhote ko mark karti hai — binding limit ($4$). Concurrency sabse chhotey bar se set hoti hai; yahan active count port count se tie karta hai.

1. Tool choose karo. Bandwidth question ⇒ crossbar formula $B_{\text{total}}=(\text{concurrent transfers})\times B$. Yeh step kyu? Word problem poochh raha hai "kitna data per second", exactly yahi crossbar tool produce karta hai; MTBF aur power tools alag sawaalon ke jawab dete hain aur apply nahi hote.
2. Concurrent transfers find karo. Teen numbers se limited — masters present (6), memory ports (4), masters actually active (4). Binding limit hai $\min (4_{\text{active}},4_{\text{ports}})=4$. Yeh step kyu? Real workloads sabse chhote se cap hote hain; yahan active-master count port count se tie karta hai, dono 4 dete hain.
3. Compute karo. $B_{\text{total}}=4\times 12=48$ GB/s. Yeh step kyu? Simultaneous transfers ko per-link bandwidth se multiply karo taaki aggregate rate sustained mile.

Verify: $48$ GB/s $\le$ theoretical peak $\min (6,4)\times 12=48$ GB/s — yeh workload memory ports saturate karta hai. Units GB/s. ✓ Agar sirf 2 masters active hote, toh $2\times 12=24$ GB/s hota.

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Example 9 — Exam twist: bandwidth aur power saath (cell K)

Forecast: zyada links = faster; energy tie ho sakti hai kyunki energy = kaam hai, time nahi.

Figure caption — power×time = area. Power-vs-time plane par do rectangles: Option A tall aur thin hai (2 W for 3 s); Option B short aur wide hai (1 W for 6 s). Unka area equal hai — dono $6$ J enclose karte hain. Picture dikhati hai ki fast option automatically energy save nahi karta: same enclosed area.

1. Transfer times. A: aggregate $4\times 8=32$ GB/s ⇒ $t_A=96/32=3$ s. B: $2\times 8=16$ GB/s ⇒ $t_B=96/16=6$ s. Yeh step kyu? Time = data ÷ bandwidth; yeh crossbar tool (aggregate GB/s) ko ek rate divide (rate → duration) ke saath combine karta hai.
2. Energy each. $E_A=(4\times 0.5\text{ W})\times 3\text{ s}=2\text{ W}\times 3=6$ J. $E_B=(2\times 0.5)\times 6=1\text{ W}\times 6=6$ J. Yeh step kyu? Energy = total power × time; sab active links count karo kyunki har link simultaneously power burn karta hai.
3. Conclude karo. Option A do guna fast hai (3 s vs 6 s) lekin dono ek jitni 6 J use karte hain. Yeh step kyu? Twist yeh hai ki speed aur energy alag sawaal hain — fast option yahan koi energy save nahi karta kyunki total kaam (bytes) aur per-byte energy equal hain. Tie-breaker hai race-to-idle: A 3 s pehle khatam karta hai aur power-gate kar sakta hai (Example 5), woh leakage save karta hai jo B abhi bhi pay kar raha hai.

Verify: $E_A=E_B=6$ J kyunki kaam fixed hai aur per-byte energy equal. $t_A=3<t_B=6$. Race-to-idle: finish karne ke baad, A gate kar sakta hai aur woh leakage save karta hai jo B abhi bhi pay karta hai. ✓ Network-on-Chip (NoC)-style bandwidth thinking ko Power Management in SoCs ke saath combine karta hai.

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Example 10 — Limiting behaviour sanity checks (cell L)

1. (a) $T_{\text{wait}}\to 0$. $e^{0/\tau }=e^0=1$, toh $\text{MTBF}\to 1/(T_0{f}_{\text{clk}}{f}_{\text{data}})$ — koi bhi synchronizer nahi hone ki raw failure rate. Matlab: zero wait = zero protection. Yeh step kyu? Confirm karta hai ki exponential unprotected baseline par collapse karta hai, jaisa hona chahiye; ek nonsense edge case formula par distrust karaata.
2. (b) $V\to 0$. $P_{\text{dyn}}=\alpha C{V}^{2}f\to 0$ quadratically. Matlab: zero voltage par logic koi dynamic power nahi jalata (aur koi kaam bhi nahi karta — yahi trade-off hai). Yeh step kyu? $V^2$ tool $V=0$ par vanish hona chahiye; karta hai, aur linear se tez, quadratic dependence confirm karta hai.
3. (c) $N\to \infty$, $M$ fixed. $\min (M,N)\to M$. Matlab: $N=M$ se aage, slaves add karne se kuch nahi milta — bandwidth $M\times B$ par saturate ho jaati hai. Yeh step kyu? $\min$ ka doosra clamp dikhata hai: eventually master side bottleneck ban jaata hai, toh formula ke dono limbs behave karte hain.

Verify: (a) $e^0=1$ ✓. (b) ${\lim }_{V\to 0}{V}^2=0$ ✓. (c) $N\ge M$ ke liye, $\min (M,N)=M$ ✓. Har tool apni boundary par sensibly degrade karta hai — koi case nahi chhoota.

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Recall Self-test (try karne ke baad reveal karo)

Crossbar $M=5,N=2,B=10$: peak aggregate? ::: $\min (5,2)\times 10=20$ GB/s. 2-flop synchronizer 32-bit bus par kyu fail karta hai? ::: Har bit mein ek tiny nonzero skew probability $p$ hoti hai; word failure $\approx 32p$, chhota lekin kabhi zero nahi → billions of transfers mein certain failure. Handshake ya async FIFO use karo. DVFS $V$ ko $20\%$ drop karta hai (frequency unchanged) — dynamic power ratio? ::: $(0.8{)}^2=0.64$, ek $36\%$ cut. Ek block jo $70\%$ time idle hai aur $0.5$ W leakage rakhta hai, overhead ignore karte hue power-gate karo — savings? ::: $0.7\times 0.5=0.35$ W. address[31:12]==0x40000 ke saath, kya 0x4000_1000 UART reach karta hai? ::: Nahi — yeh 0x40001 tak shift karta hai; yeh GPIO ka hai (half-open interval UART ka end exclude karta hai).

Related depth: AMBA Bus Standards, AXI Protocol, Physical Design Flow, Formal Verification Methods.