6.3.9 · D2 · HinglishInterconnects, Buses & SoC

Visual walkthroughSystem-on-Chip (SoC) integration

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6.3.9 · D2 · Hardware › Interconnects, Buses & SoC › System-on-Chip (SoC) integration

Yeh page System-on-Chip (SoC) integration ka sabse zyada use hone wala number rebuild karta hai: ek crossbar interconnect ki peak bandwidth,

Parent note ne yeh bataya tha. Yahan hum ise kama ke dikhate hain — ek picture at a time. End tak tumhe exactly pata hoga ki har symbol ka kya matlab hai, formula mein min kyun hai aur plus ya times kyun nahi, aur har awkward case mein kya hota hai (ek master, ek slave, sab ek hi memory ke liye lad rahe hain).


KYA HAI. Kisi bhi formula se pehle, hum har piece ko naam dete hain aur uski picture banate hain. Ek master woh block hai jo data transfer shuru karta hai (woh kahta hai "address X padho" ya "yeh likho"). Ek slave woh block hai jo respond karta hai (memory, ek peripheral). Ek link wires ka ek physical set hai jo data carry kar sakta hai.

KYUN. Jab tak tumhe pata na ho ki kitni sadakein hain aur unpar kaun ja sakta hai, tab tak tum trucks nahi gin sakte. Neech diye gaye har symbol ko is ek drawing par define kiya gaya hai taaki baad mein kuch bhi mystery na rahe.

PICTURE. Left side par masters (blue). Right side par slaves (pink). Har master ke paas bahar jaata ek link hai; har slave ke paas andar aata ek link hai.

Figure — System-on-Chip (SoC) integration

Step 2 — "Crossbar" kya hota hai? Full connectivity

KYA HAI. Ek crossbar ek aisa interconnect hai jahan har master har slave tak pahunch sakta hai, aur kai pairs ek saath baat kar sakte hain. Ek sadakon ke grid ki tarah socho: horizontal wires (har master ke liye ek) vertical wires (har slave ke liye ek) ko cross karti hain, aur har intersection par ek switch hai.

Crossbar kyun use karein, ek single shared bus nahin? Shared bus ek akeli sadak hai jis par sab queue mein lagte hain — ek waqt par sirf ek transfer. Crossbar iski ulti extreme hai: har crossing par ek switch banao taaki alag-alag conversations ek doosre ko block na karein. Hum uske liye area kharcha karte hain (cost Step 8 mein), lekin parallelism khareedte hain.

PICTURE. Neechla grid. Row , column par ek filled dot ka matlab hai "master abhi slave se connected hai." Dhyan do ki har row mein zyada se zyada ek dot jal sakta hai, aur har column mein zyada se zyada ek dot jal sakta hai — yahi constraint poori derivation hai.

Figure — System-on-Chip (SoC) integration

Step 3 — Best case mein trucks gino (masters, slaves se kam hain)

KYA HAI. Maano (bhejne waalon se zyada destinations hain). Poochho: ek saath maximum kitne transfers ho sakte hain? Kyunki har master ke paas exactly ek link hai aur sab alag-alag slaves choose karte hain, har master ek saath move kar sakta hai.

KYUN. Hum peak chahte hain — woh ceiling performance jo fabric kabhi bhi hit kar sakti hai. Toh hum sabse friendly traffic maante hain: do masters ek hi slave nahi chahte. Koi ladhna nahi.

PICTURE. Chaar masters, lekin yahan : har blue arrow apne pink slave par utarta hai. Green (active) arrows gino.

Figure — System-on-Chip (SoC) integration

Har master busy hai, har ek contribute kar raha hai, toh hum unhe simply jod dete hain: ke copies.


Step 4 — Doosri taraf: masters se kam slaves

KYA HAI. Ab palto: (destinations se zyada senders hain). Sabse friendly traffic mein bhi, tum se zyada dots nahi jala sakte, kyunki sirf columns (slaves) hain, aur har column mein ek dot hai.

KYUN. Slaves ab bottleneck hain. Extra masters ke paas koi free nahi jisse baat karein — kuch ko intezaar karna padega. Parallelism us side se cap ho jaata hai jo chhoti hai.

PICTURE. Paanch masters, teen slaves. Ek saath sirf teen arrows green ho sakte hain; do masters (greyed) ruk jaate hain.

Figure — System-on-Chip (SoC) integration


Step 5 — min se dono cases ko mila do

KYA HAI. Step 3 ne diya jab ; Step 4 ne diya jab . Dono ek hi cheez keh rahe hain: ek saath transfers ki sankhya aur mein se jo chhota hai, woh hai. "Chhota" ka matlab exactly hai.

min kyun, + ya \times kyun nahi?

  • $M+B$ nahi — hum count kar rahe hain kitne links ek saath chalte hain ( ya ), phir har ek carry karta hai. Parallel links ki bandwidths add hoti hain, isliye ke saath ek product milta hai, ke saath sum nahi.
  • $M\times N \times B$ nahi — uske liye har master ko har slave se ek saath baat karni padti, lekin ek master ke paas ek link hai. Impossible hai.
  • $\min$ sahi limiter choose karta hai: funnel ka narrow side.

PICTURE. Ek funnel view — left par pipes, right par pipes; throughput narrow end se throttle hota hai.

Figure — System-on-Chip (SoC) integration

Kyunki jab aur warna, yeh ek line dono earlier cases ko ek saath reproduce karti hai.


Step 6 — Worst case: sab ek hi slave chahte hain

KYA HAI. Peak ne alag-alag destinations maane the. Ab sabse nasty traffic: saare masters slave 0 ko target karte hain. Woh column sirf ek dot rakh sakta hai, isliye transfers ek ke baad ek (serialized) hone chahiye. Peak ek single link tak gir jaati hai.

KYUN dikhayein? Kyunki "peak" ek promise hai jo fabric rarely rakhta hai. Real programs mein hotspots hote hain (sab DRAM padhte hain). Ek designer ko ceiling aur floor dono pata honi chahiye.

PICTURE. Sab masters slave 0 par aim karte hain. Ek waqt par sirf ek green arrow; baaki queue mein. Ek arbiter (peela referee) decide karta hai kiski baari hai.

Figure — System-on-Chip (SoC) integration


Step 7 — Degenerate cases (koi bhi scenario bina dikhaaye mat chhodna)

KYA HAI. mein chhote numbers daal kar check karo ki kuch toot toh nahi raha.

Case Matlab
Single master, single slave 1 1 Crossbar ek wire mein degenerate ho jaata hai — koi parallelism possible nahi.
Ek master, kai slaves 1 8 Ek sender ek waqt par sirf ek link use kar sakta hai, isliye extra slaves uski bandwidth mein madad nahi karte.
Kai masters, ek slave 8 1 Worst case jaisa hi — akela slave funnel hai.
Zero masters 0 5 Koi nahi bhejta → koi traffic nahi. Formula deta hai, sahi hai.

KYUN. Ek formula jis par tum trust karte ho, usse apni edges survive karni chahiye. Dhyan do inhe gracefully handle karta hai: jab bhi koi bhi side 1 (ya 0) ho, bandwidth (ya 0) hai. Koi special-casing zaroori nahi.

PICTURE. Charon degenerate wirings side by side.

Figure — System-on-Chip (SoC) integration

Step 8 — Humne jo cost diya, aur worked numbers

KYA HAI. Crossbar ki parallelism free nahi hai. Ek full switch grid mein har (master, slave) pair ke liye ek intersection hai, isliye area (aur power) ki tarah badhta hai. Isliye parent note ne kaha "cost ki tarah badhta hai" aur isliye bahut bade chips Network-on-Chip par switch karte hain.

Bandwidth () aur cost () mein contrast kyun karein? Tension poora design decision hai: tum bandwidth gain karte ho lekin silicon pay karte ho. Dono sides double karne par peak bandwidth double hoti hai lekin area quadruple ho jaata hai.

Worked example (parent ke numbers, ab fully derived): (CPU, GPU, DMA, DSP), (DRAM, Flash, peripherals), GB/s.

  • Peak: GB/s (teen alag slaves ek saath busy; 4th master wait karta hai).
  • Worst: sab DRAM hit karte hain GB/s.
  • Switch cost: crossing points.

PICTURE. Bandwidth (green, ke saath chalti hai) vs. area cost (yellow, ke saath chalti hai) jaise chip se tak scale hota hai. Dekho yellow curve green ko kaise peeche chhodti hai.

Figure — System-on-Chip (SoC) integration

Ek-picture summary

Upar sab kuch, compress kiya gaya: funnel parallel links deta hai, har ek ka; friendly traffic ceiling hit karti hai, one-hot-slave traffic floor hit karti hai; aur silicon bill ki tarah badhta hai.

Figure — System-on-Chip (SoC) integration
Recall Feynman retelling — ise plain words mein wapas bolo

Crossbar ek switchboard hai: ek taraf senders, doosri taraf receivers, aur koi bhi sender kisi bhi receiver se patch ho sakta hai. Lekin har sender ke paas sirf ek plug hai aur har receiver ke paas sirf ek socket. Toh simultaneous calls ki sankhya kabhi chhote group se zyada nahi ho sakti — yahi hai. Ek line kitna carry karti hai, , se multiply karo, aur tumhare paas best-ever bandwidth hai. Agar sab ek hi receiver dial karein, toh woh queue mein lagte hain aur tum ek single line ki value, , par wapas aa jaate ho. Pakda yeh hai: "any-to-any" banane ke liye har crossing par ek switch chahiye, isliye hardware bill ki tarah scale karta hai — chip badhao aur cost speed se kahin tez balloon hoti hai, isliye bahut bade chips crossbar chhodkar packet-switched network on chip use karte hain.

Recall

mein min ka physically kya matlab hai? ::: Ek saath chal sakne wale transfers ki maximum sankhya chhote side se limit hoti hai — na masters se zyada parallel conversations ho sakti hain, na slaves se zyada. Yeh kyun hai, kyun nahi? ::: Har parallel link independently GB/s carry karta hai; parallel bandwidths add hoti hain, isliye links dete hain jahan . ke liye best case vs worst case? ::: Best GB/s (teen alag slaves), worst GB/s (sab ek slave ko target karte hain). Bade SoCs crossbar kyun chhodते hain? ::: Switch area/power ki tarah badhta hai, isliye cost bandwidth gain se kahin tez explode hoti hai.

Related vault topics: AXI Protocol · AMBA Bus Standards · Network-on-Chip (NoC) · Clock Domain Crossing Techniques · Power Management in SoCs · Physical Design Flow · Formal Verification Methods