Foundations — System-on-Chip (SoC) integration

6.3.9 · D1 · Hardware › Interconnects, Buses & SoC › System-on-Chip (SoC) integration

Is page par kuch bhi assume nahi kiya gaya. Parent note padhne se pehle, tumhe uske har word aur symbol ka maalik hona chahiye. Hum inhe order mein build karte hain, har ek apne neeche ki picture se.

0. Stage: "a chip" physically kya hota hai

Yeh pehle kyun zaroori hai: ek SoC ka har advantage — lower latency, lower power — is baat se aata hai ki wires chhoti hain aur die par hi rehti hain. Die ko chodna (figure mein red arrow) distance, power, aur time costs karta hai. Yeh picture yaad rakho; poora topic hai "ise box ke andar rakho".

1. Transistor → gate → register: timing ke atoms

Topic ko yeh kyun chahiye: parent note ka poora "Clock Domain Crossing" section registers ke galat instant par sampling karne ke baare mein hai. Tum metastability tab tak nahi samajh sakte jab tak yeh na dekho ki ek register apni input ko sirf clock ke rising edge par dekhta hai (figure mein yellow tick), aur chahta hai ki input us edge ke aas-paas still rahe.

2. Frequency $f$ aur period $T$ — heartbeat symbols

Parent note ki line uart_clk = cpu_clk / 20 matlab: CPU ke fast heartbeat lo aur har 20 ticks mein se 19 skip karo, ek heartbeat produce karo jo $20\times$ slower ho. $1\text{GHz}/20=50\text{MHz}$.

3. Setup/hold window aur metastability — clocks cross karna dangerous kyun hai

Topic ko yeh kyun chahiye: alag clocks par do IP blocks unrelated instants par tick karte hain. Clock-A se ek signal clock-B ke register par forbidden window ke andar aa sakta hai (figure mein red zone). Yeh unavoidable hai — tum unrelated clocks ko align nahi kar sakte — isliye tum synchronizers se ise manage karte ho.

4. MTBF aur symbols $\tau$, $\alpha$, $C$, $V$, $f$

Parent note kai Greek aur single-letter symbols use karta hai. Yahan har ek, zero se.

Ab power symbols:

5. Bits, bytes, buses aur bandwidth $B$

Topic ko yeh kyun chahiye: crossbar formula $B_{\text{total}}=\min (M,N)\times B$ tab hi samajh aata hai jab tum jaano ki $B$ per link hai, $M$ data sources ki number hai, aur $N$ destinations ki. Figure dikhata hai ki $\min (M,N)$ kyun aata hai — narrow side bottleneck hai, jaise paani pipes ki do rows mein se fewer ke through.

6. Hexadecimal aur address map

7. Voltage levels aur crossing symbols (1.2 V vs 0.9 V)

Yeh Power Management in SoCs ke peeche physical machinery hain.

Prerequisite map

Equipment checklist

Right side cover karo aur aloud jawab do — sirf confirm karne ke liye reveal karo.