Foundations — DMA controllers

This page assumes you know nothing. Before we can read a single line of the parent note, we must build every word and symbol it throws at us. We go slow, in order, each idea leaning on the one before it. Read top to bottom.

1. Memory — the giant numbered locker wall

Look at the figure. The boxes are drawn as a line of lockers. The address is written under each locker (0, 1, 2, …) — it never changes, it's just the locker's house-number. The contents are written inside — those change when you write.

Why the topic needs this: a DMA transfer is nothing but "copy the contents of these lockers into those lockers." Every register we meet later just stores a locker number or how many lockers.

You'll meet this same idea again in Memory-Mapped IO and SDRAM Controllers.

2. Hexadecimal — why addresses look like 0x1000

The parent note writes addresses like 0x1000. That's just a number in a different costume.

Why engineers use it: memory addresses are really long strings of on/off bits, and hex packs exactly 4 bits into one hex digit, so it's the shortest tidy way to write them.

3. Bit and byte width — 1, 2, or 4 boxes at once

Why the topic needs this: if you move 4 boxes per step, you finish 4× faster, but you must also jump the address forward by 4 each step, not 1. That jump number is exactly the width. Hold this — it explains the "SAR += width" line later.

4. The CPU — the worker who runs instructions

That last sentence is the whole reason DMA exists. If the CPU is busy carrying bytes, it can't do anything else. The parent note's "25 milliseconds wasted" is just: 5 million tiny carry-instructions × how long each takes.

5. The bus — the shared road

Look at the figure: CPU, DMA helper, memory, and a disk all hang off the same road. Crucial fact: only one device can drive the road at any instant — like a single-lane bridge. This single-lane rule is the source of every "arbitration", "burst vs. cycle-stealing", and "CPU starvation" idea in the parent note.

Deeper detail lives in Bus Architecture, PCIe, and ARM AMBA AXI.

6. Bus master — who is allowed to drive

Normally the CPU is the master. The key trick of DMA: the DMA controller is also able to become master. That's what "the DMA controller is a bus master" means in the parent note — it can seize the single-lane bridge and steer traffic itself.

7. Request / grant — asking to drive

Because only one master may drive, there must be a polite handshake before the DMA takes over.

Follow the numbered arrows in the figure: (1) DMA asserts BR, (2) arbiter answers BG, (3) DMA drives the bus, (4) DMA drops BR, (5) CPU resumes. This exact loop is the parent note's "State 1 (REQUEST)".

8. Register — a tiny named box inside a chip

Why exactly these four? To copy autonomously the helper must know from where (SAR), to where (DAR), how much (BCR), and how (CSR). Remove any one and the transfer is impossible. That is the parent's "derivation of necessity."

9. Auto-increment — the pointer that walks forward

$\text{SAR}\leftarrow \text{SAR}+w,\text{DAR}\leftarrow \text{DAR}+w,\text{BCR}\leftarrow \text{BCR}-w$

Here $w$ is the width from Section 3, and $\leftarrow$ means "becomes / is replaced by".

Picture two fingers sliding along the locker wall, one on the source row, one on the destination row, both stepping right by $w$ boxes each tick, while a counter (BCR) ticks down toward zero. When the counter hits zero, the whole job is finished. This is why BCR is the "termination condition."

10. The ≠ and = tests — how it knows when to stop

The parent's state machine writes If BCR ≠ 0 and If BCR = 0.

So "$\text{BCR}\ne 0$ → keep going" reads "if bytes-left is not zero, do another step." A tiny hardware circuit called a comparator checks this every tick. No software, no CPU — pure logic gates.

11. Interrupt — the "I'm finished!" tap on the shoulder

Why not just have the CPU keep checking? Because checking (called polling) wastes the very CPU time DMA was meant to save. An interrupt lets the CPU stay busy until the exact instant it's needed.

Full treatment in Interrupts. In hardware you'll also meet interrupt-driven devices like a UART.

12. Cache & coherency — the sneaky private notebook

The parent note lists Cache Coherency as related. One sentence of foundation:

You don't need to master this yet — just know the word means "cache copy and real memory must agree."

Prerequisite map

Every arrow means "you must understand the left box before the right box makes sense." All roads feed into DMA Controller — the parent topic.

Equipment checklist

Test yourself — cover the right side and try to answer each before revealing.

Once every reveal above feels obvious, you're ready to read the parent note line by line: DMA controllers.