Foundations — DMA controllers

6.3.8 · D1 · Hardware › Interconnects, Buses & SoC › DMA controllers

Is page pe assume kiya gaya hai ki aap kuch nahi jaante. Parent note ki ek bhi line padhne se pehle, humein har ek word aur symbol build karna hoga jo woh humpar throw karta hai. Hum slow chalte hain, order mein, har idea apne pehle wale idea pe lean karta hua. Top se bottom tak padho.

1. Memory — woh giant numbered locker wall

Figure dekho. Boxes ek line of lockers ki tarah draw kiye gaye hain. Address har locker ke neeche likha hai (0, 1, 2, …) — yeh kabhi nahi badlta, yeh bas locker ka house-number hai. Contents andar likhe hain — woh tab badle jaate hain jab aap write karte ho.

Topic ko yeh kyun chahiye: ek DMA transfer kuch nahi hai siwaaye "in lockers ka content un lockers mein copy karo." Jo bhi registers hum baad mein milenge woh sirf ek locker number ya kitne lockers store karte hain.

Yahi idea aapko Memory-Mapped IO aur SDRAM Controllers mein dobara milega.

2. Hexadecimal — addresses 0x1000 jaisi kyun dikhti hain

Parent note addresses 0x1000 jaisi likhta hai. Yeh bas ek number hai alag costume mein.

Engineers ise kyun use karte hain: memory addresses actually bits ki bahut lambi strings hoti hain, aur hex exactly 4 bits ko ek hex digit mein pack karta hai, isliye yeh unhe likhne ka sabse chhota tidy tarika hai.

3. Bit aur byte width — ek baar mein 1, 2, ya 4 boxes

Topic ko yeh kyun chahiye: agar aap 4 boxes per step move karte ho, toh 4× faster khatam hoga, lekin aapko address bhi 4 aage jump karna hoga har step mein, 1 nahi. Woh jump number bilkul width ke barabar hai. Yeh yaad rakho — yeh baad mein "SAR += width" wali line explain karta hai.

4. CPU — woh worker jo instructions run karta hai

Woh aakhri sentence hi poora reason hai DMA ke existence ka. Agar CPU bytes carry karne mein busy hai, toh woh aur kuch nahi kar sakta. Parent note ka "25 milliseconds wasted" bas yahi hai: 50 lakh tiny carry-instructions × har ek mein kitna time lagta hai.

5. Bus — woh shared road

Figure dekho: CPU, DMA helper, memory, aur ek disk sab usi road pe hang karte hain. Crucial fact: sirf ek device kisi bhi instant mein road drive kar sakta hai — jaise ek single-lane bridge. Yeh single-lane rule hi har "arbitration", "burst vs. cycle-stealing", aur "CPU starvation" idea ka source hai parent note mein.

Zyada detail Bus Architecture, PCIe, aur ARM AMBA AXI mein hai.

6. Bus master — drive karne ki permission kise hai

Normally CPU master hota hai. DMA ka key trick: DMA controller bhi master ban sakta hai. Iska matlab yahi hai parent note mein "DMA controller ek bus master hai" — woh single-lane bridge seize kar sakta hai aur traffic khud steer kar sakta hai.

7. Request / grant — drive karne ke liye poochha

Kyunki sirf ek master drive kar sakta hai, DMA ke takeover se pehle ek polite handshake zaroori hai.

Figure mein numbered arrows follow karo: (1) DMA BR assert karta hai, (2) arbiter BG se jawab deta hai, (3) DMA bus drive karta hai, (4) DMA BR drop karta hai, (5) CPU resume karta hai. Yahi exact loop parent note ka "State 1 (REQUEST)" hai.

8. Register — chip ke andar ek chota named box

Exactly yeh chaar kyun? Autonomously copy karne ke liye helper ko pata hona chahiye kahan se (SAR), kahan (DAR), kitna (BCR), aur kaise (CSR). Koi ek hatao aur transfer impossible ho jaata hai. Yahi parent ka "derivation of necessity" hai.

9. Auto-increment — woh pointer jo aage chalta hai

$\text{SAR}\leftarrow \text{SAR}+w,\text{DAR}\leftarrow \text{DAR}+w,\text{BCR}\leftarrow \text{BCR}-w$

Yahan $w$ Section 3 ka width hai, aur $\leftarrow$ ka matlab hai "ban jaata hai / replace ho jaata hai".

Locker wall ke saath slide karte do fingers imagine karo, ek source row pe, ek destination row pe, dono $w$ boxes seedhe har tick pe step karte hue, jabki ek counter (BCR) zero ki taraf down tick karta hai. Jab counter zero hit karta hai, poora kaam khatam. Isliye BCR "termination condition" hai.

10. ≠ aur = tests — yeh kaise jaanta hai kab rukna hai

Parent ka state machine If BCR ≠ 0 aur If BCR = 0 likhta hai.

Toh "$\text{BCR}\ne 0$ → chalte raho" padha jaata hai "agar bytes-left zero nahi hai, ek aur step karo." Ek chota hardware circuit jise comparator kehte hain har tick yeh check karta hai. Koi software nahi, koi CPU nahi — pure logic gates.

11. Interrupt — woh "main khatam!" wala kandhe pe thapki

CPU ko baar baar check karne kyun nahi dete? Kyunki checking (jise polling kehte hain) usi CPU time ko waste karta hai jo DMA save karne ke liye bana tha. Ek interrupt CPU ko busy rehne deta hai us exact instant tak jab uski zaroorat ho.

Poori treatment Interrupts mein hai. Hardware mein aap interrupt-driven devices bhi milenge jaise UART.

12. Cache & coherency — woh chhupi hui private notebook

Parent note Cache Coherency ko related list karta hai. Foundation ka ek sentence:

Abhi aapko yeh master nahi karna — bas jaano ki word ka matlab hai "cache copy aur real memory mein agree hona chahiye."

Prerequisite map

Har arrow ka matlab hai "right box samajhne se pehle left box samajhna zaroori hai." Saari roads DMA Controller mein feed hoti hain — woh parent topic.

Equipment checklist

Khud test karo — right side cover karo aur reveal karne se pehle har ek ka jawab dene ki koshish karo.

Jab bhi upar ka har reveal obvious lagey, tab aap parent note line by line padhne ke liye ready hain: DMA controllers.