DMA controllers: Exercises — Hardware deep dive

This page is a self-test ladder. Every exercise builds on the parent note DMA controllers and the machinery it defined — the four registers ( $SAR$ , $DAR$ , $BCR$ , $CSR$ ), the three transfer modes (burst, cycle-stealing, transparent), and the timing formulas. If a symbol below is unfamiliar, it was defined in the parent; this page uses it, it does not re-derive it.

Before you start, let us pin down the two timing formulas you will lean on the most, so we never write a symbol we did not earn.

Level 1 — Recognition

Exercise 1.1 (L1)

A DMA controller has four per-channel registers. For a transfer that copies 2048 bytes from address 0x2000_0000 to 0x3000_0000, using 32-bit (word) width, state the initial value each register should hold, and say which one the CPU sets last to launch the transfer.

Recall Solution

$SAR = 0x2000_0000$ — the source (where to read).
$DAR = 0x3000_0000$ — the destination (where to write).
$BCR = 2048$ — the byte count (the countdown that terminates the transfer). Note it is bytes, not words, so it holds $2048$ , not $512$ .
$CSR$ — mode bits (width $= 10$ for word, direction, increment bits). Its EN bit (bit 0) is written last: flipping EN to $1$ is the hardware signal that activates the transfer state machine. Set it first and the DMA would fire before the addresses are valid.

Exercise 1.2 (L1)

Given the parent's CSR layout, what value goes in bits 4–5 (Direction) to move data from a peripheral into memory (P2M), and what value in bits 2–3 (Transfer Width) for a halfword?

Recall Solution

Direction P2M $= 10$ (binary $2$ ).
Halfword width $= 01$ (binary $1$ ).

Level 2 — Application

Exercise 2.1 (L2)

Transfer 8 KB at 32-bit width on a 200 MHz bus in burst mode. Setup $T_{setup} = 5$ cycles, $T_{cycle} = 1$ cycle. Find $N$ , total cycles, and total time in microseconds.

Recall Solution

$8 KB = 8192$ bytes. Width $= 4$ bytes, so $N = \frac{8192}{4} = 2048 transfers .$ Cycles: $T_{burst} = 5 + 2048 \times 1 = 2053$ cycles. One cycle at $200 MHz$ is $\frac{1}{200 \times 1 0 ^{6}} = 5 ns$ . So $T_{burst} = 2053 \times 5 ns = 10265 ns = 10.265 μ s .$

Exercise 2.2 (L2)

Same 8 KB, 32-bit, 200 MHz transfer, but in cycle-stealing mode with $T_{arb} = 3$ and $T_{transfer} = 1$ cycles. Find total time, and the slowdown factor versus the burst result of Ex 2.1.

Recall Solution

$N = 2048$ (unchanged). $T_{steal} = 2048 \times (3 + 1) = 8192 cycles = 8192 \times 5 ns = 40960 ns = 40.96 μ s .$ Slowdown $= \frac{40960}{10265} \approx 3.99 \times$ (essentially $4 \times$ ).

Level 3 — Analysis

Exercise 3.1 (L3)

A CPU shares a 100 MHz bus with a DMA engine. The CPU issues one bus access every $6$ cycles (the other $5$ are internal/cache work). A transparent-mode DMA sneaks a transfer into each idle bus cycle. Over a $6$ -cycle CPU window, how many cycles are free for DMA, and what effective DMA throughput (bytes/s) does this give at 32-bit width?

Recall Solution

In each $6$ -cycle window the CPU uses $1$ cycle, leaving $5$ free cycles for transparent DMA. DMA duty cycle $= \frac{5}{6}$ . If a transfer takes $1$ cycle, DMA completes $\frac{5}{6}$ transfers per cycle on average. Transfers per second $= \frac{5}{6} \times 100 \times 1 0^{6} = 8.333 \times 1 0^{7}$ transfers/s. At $4$ bytes each: $Throughput = 8.333 \times 1 0^{7} \times 4 = 3.333 \times 1 0^{8} bytes/s \approx 333.3 MB/s .$

Exercise 3.2 (L3)

Three DMA masters — Disk, Network, Audio — share a bus under fixed priority Disk > Network > Audio. Disk requests continuously and each of its bursts holds the bus $1000$ cycles. Explain quantitatively why Audio can starve, and how round-robin rescues it. Assume all three always have work.

Recall Solution

Fixed priority: the grant always goes to the highest requester still asking. Disk asks continuously, so after each $1000$ -cycle burst it immediately re-requests and wins again. Network and Audio never see a grant → their wait time is unbounded (infinite). Audio starves. Round-robin: after a master uses the bus, its priority drops to the bottom via $(i + 1) mod N$ . So the grant order becomes Disk → Network → Audio → Disk → … Each master waits at most the other two bursts. With $N = 3$ masters and $1000$ -cycle bursts, Audio's worst-case wait is $2 \times 1000 = 2000 cycles,$ and it is guaranteed the bus once every $3000$ cycles. Its bus share is $\frac{1}{3} \approx 33.3%$ , finite and fair.

Level 4 — Synthesis

Exercise 4.1 (L4)

You must stream from an SSD at a sustained 3.0 GB/s into RAM on a 64-bit (8-byte) bus. The DMA can run burst or cycle-stealing; cycle-stealing has $T_{arb} = 3$ , $T_{transfer} = 1$ per transfer; burst has $T_{cycle} = 1$ and negligible setup. Find the minimum bus frequency $f_{bus}$ needed for each mode to keep up. Which mode is feasible on a $500 MHz$ bus?

Recall Solution

Required transfer rate in transfers/s (8 bytes each): $R = \frac{3.0 \times 1 0 ^{9} B/s}{8 B} = 3.75 \times 1 0^{8} transfers/s .$ Burst: $1$ cycle per transfer, so we need $\geq 3.75 \times 1 0^{8}$ cycles/s: $f_{burst} \geq 375 MHz .$ Cycle-stealing: $T_{arb} + T_{transfer} = 4$ cycles per transfer: $f_{steal} \geq 4 \times 3.75 \times 1 0^{8} = 1.5 \times 1 0^{9} = 1500 MHz = 1.5 GHz .$ On a $500 MHz$ bus: burst needs $375 MHz$ ✓ (feasible, with headroom), cycle-stealing needs $1.5 GHz$ ✗ (impossible). Use burst mode.

Exercise 4.2 (L4)

On that same 3 GB/s burst stream (feasible on the $500 MHz$ bus), a burst holds the bus for 1024 transfers. During each burst, the CPU is fully blocked. If the CPU also needs the bus and can tolerate at most 2 µs of blocking at a time, does a single burst violate this? If so, what maximum burst length keeps blocking under $2 μ s$ ?

Recall Solution

At $500 MHz$ , one cycle $= 2 ns$ . A $1024$ -transfer burst (1 cycle each) $= 1024 \times 2 ns = 2048 ns = 2.048 μ s$ . That exceeds $2 μ s$ — the CPU is blocked too long. Max transfers under $2 μ s$ : $\frac{2000 ns}{2 ns} = 1000$ transfers. So set burst length $\leq 1000$ transfers (the parent's CSR burst field holds 0–255, so in practice you would program bursts of $\leq 255$ and let the engine chain them). Programming e.g. $256$ -transfer bursts blocks only $256 \times 2 ns = 512 ns$ , comfortably under the limit.

Level 5 — Mastery

Exercise 5.1 (L5)

Design decision. A system has: (a) a real-time UART UART receiver that drips 1 byte every $10 μ s$ and cannot tolerate a lost byte, and (b) a bulk PCIe PCIe transfer of $16 MB$ that wants maximum throughput. The bus is $250 MHz$ , 32-bit. Choose a transfer mode for each DMA channel, justify with numbers, and state the priority scheme. Consider the interaction with Interrupts and Cache Coherency.

Recall Solution

UART channel → cycle-stealing (or single-transfer). It needs only $1$ byte per $10 μ s$ — a rate of $1 0^{5}$ B/s, trivially met even with per-transfer arbitration ( $4$ cycles $= 16 ns$ per byte on a $250 MHz$ bus). What it cannot tolerate is latency: if a long burst holds the bus, the UART's 1-byte FIFO overflows and a byte is lost. Cycle-stealing releases the bus after each transfer, guaranteeing the UART prompt service.

PCIe channel → burst mode. $16 MB = 16, 777, 216$ bytes, $\div 4 = 4, 194, 304$ transfers. In burst at $1$ cycle each, $4 ns$ /cycle → $4, 194, 304 \times 4 ns \approx 16.78 ms$ . Cycle-stealing ( $4$ cycles) would take $\approx 67 ms$ — 4× worse. Bulk data wants burst.

Priority: give UART higher priority (fixed priority UART > PCIe) so its rare, latency-critical requests preempt bulk bursts. Because the UART requests only every $10 μ s$ and holds the bus $\sim 16 ns$ , it steals a negligible $0.16%$ of bus time — PCIe barely notices. But limit PCIe burst length (Ex 4.2 logic) so it checks in often enough that a UART request never waits more than one short burst.

Interrupts: the PCIe channel sets $CSR.IE = 1$ so completion of the 16 MB block raises one interrupt (not one per byte) — the whole point of DMA over programmed I/O. The UART channel may use per-buffer completion interrupts.

Cache coherency: DMA writes to RAM behind the CPU's cache. After the PCIe DMA finishes, the CPU's cached copy of those addresses is stale. Either the interconnect must snoop/invalidate (hardware coherency, cf. ARM AMBA AXI ACE) or the driver must invalidate the cache range before reading the DMA'd data. Skip this and the CPU reads old garbage.

Recall Numeric summary

UART rate need: $1 0^{5}$ B/s; per-byte cost $16 ns$ ⇒ effortless.
PCIe burst time: $\approx 16.78 ms$ ; cycle-steal: $\approx 67.1 ms$ (4×).
UART bus occupancy at 1 byte/ $10 μ s$ : $\frac{16 ns}{10000 ns} = 0.16%$ .

Related: Bus Architecture · Memory-Mapped IO · SDRAM Controllers · DMA controllers