DMA controllers: Exercises — Hinglish deep dive

6.3.8 · D4 · Hardware › Interconnects, Buses & SoC › DMA controllers

Yeh page ek self-test ladder hai. Har exercise parent note DMA controllers par aur usmein define ki gayi machinery par build hoti hai — char registers ( $SAR$ , $DAR$ , $BCR$ , $CSR$ ), teen transfer modes (burst, cycle-stealing, transparent), aur timing formulas. Agar koi symbol neeche unfamiliar lage, toh woh parent mein define kiya gaya tha; yeh page uss symbol ko use karti hai, re-derive nahi karti.

Shuru karne se pehle, aao hum woh do timing formulas pin down kar lein jinpar tum sabse zyada lean karoge, taaki hum koi aisa symbol kabhi na likhein jo humne earn na kiya ho.

Level 1 — Recognition

Exercise 1.1 (L1)

Ek DMA controller mein per-channel char registers hain. Ek aisi transfer ke liye jo 2048 bytes ko address 0x2000_0000 se 0x3000_0000 tak copy karti hai, 32-bit (word) width use karke, batao ki har register mein kaunsi initial value honi chahiye, aur CPU last mein kaun sa register set karta hai transfer launch karne ke liye.

Recall Solution

$SAR = 0x2000_0000$ — source (kahaan se padhna hai).
$DAR = 0x3000_0000$ — destination (kahaan likhna hai).
$BCR = 2048$ — byte count (woh countdown jo transfer terminate karta hai). Dhyan raho yeh bytes hai, words nahi, isliye yeh $2048$ hold karta hai, $512$ nahi.
$CSR$ — mode bits (width $= 10$ word ke liye, direction, increment bits). Iska EN bit (bit 0) last mein likha jaata hai: EN ko $1$ karna woh hardware signal hai jo transfer state machine ko activate karta hai. Pehle set karo toh DMA fire ho jaayega addresses valid hone se pehle.

Exercise 1.2 (L1)

Parent ke CSR layout ko dekhte hue, bits 4–5 (Direction) mein kaunsi value jaati hai data ko peripheral se memory mein (P2M) move karne ke liye, aur bits 2–3 (Transfer Width) mein halfword ke liye kaunsi value?

Recall Solution

Direction P2M $= 10$ (binary $2$ ).
Halfword width $= 01$ (binary $1$ ).

Level 2 — Application

Exercise 2.1 (L2)

8 KB transfer 32-bit width par, 200 MHz bus par burst mode mein. Setup $T_{setup} = 5$ cycles, $T_{cycle} = 1$ cycle. $N$ , total cycles, aur total time microseconds mein nikalo.

Recall Solution

$8 KB = 8192$ bytes. Width $= 4$ bytes, toh $N = \frac{8192}{4} = 2048 transfers .$ Cycles: $T_{burst} = 5 + 2048 \times 1 = 2053$ cycles. $200 MHz$ par ek cycle $= \frac{1}{200 \times 1 0 ^{6}} = 5 ns$ hai. Toh $T_{burst} = 2053 \times 5 ns = 10265 ns = 10.265 μ s .$

Exercise 2.2 (L2)

Wohi 8 KB, 32-bit, 200 MHz transfer, lekin cycle-stealing mode mein $T_{arb} = 3$ aur $T_{transfer} = 1$ cycles ke saath. Total time nikalo, aur Ex 2.1 ke burst result ke muqable slowdown factor bhi nikalo.

Recall Solution

$N = 2048$ (unchanged). $T_{steal} = 2048 \times (3 + 1) = 8192 cycles = 8192 \times 5 ns = 40960 ns = 40.96 μ s .$ Slowdown $= \frac{40960}{10265} \approx 3.99 \times$ (essentially $4 \times$ ).

Level 3 — Analysis

Exercise 3.1 (L3)

Ek CPU ek 100 MHz bus share karta hai ek DMA engine ke saath. CPU har $6$ cycles mein ek bus access issue karta hai (baaki $5$ internal/cache work hain). Ek transparent-mode DMA har idle bus cycle mein ek transfer sneak karta hai. Ek $6$ -cycle CPU window mein, DMA ke liye kitne cycles free hain, aur 32-bit width par kaunsa effective DMA throughput (bytes/s) milta hai?

Recall Solution

Har $6$ -cycle window mein CPU $1$ cycle use karta hai, baaki $5$ cycles transparent DMA ke liye free rehti hain. DMA duty cycle $= \frac{5}{6}$ . Agar ek transfer $1$ cycle leta hai, toh DMA average par $\frac{5}{6}$ transfers per cycle complete karta hai. Transfers per second $= \frac{5}{6} \times 100 \times 1 0^{6} = 8.333 \times 1 0^{7}$ transfers/s. $4$ bytes each par: $Throughput = 8.333 \times 1 0^{7} \times 4 = 3.333 \times 1 0^{8} bytes/s \approx 333.3 MB/s .$

Exercise 3.2 (L3)

Teen DMA masters — Disk, Network, Audio — fixed priority Disk > Network > Audio ke saath bus share karte hain. Disk continuously request karta hai aur uska har burst bus ko $1000$ cycles hold karta hai. Quantitatively explain karo kyun Audio starve kar sakta hai, aur round-robin use kaise bachaata hai. Maano teeno hamesha kaam mein hain.

Recall Solution

Fixed priority: grant hamesha sabse oonche requester ko jaata hai jo abhi bhi maang raha hai. Disk continuously maangta hai, toh har $1000$ -cycle burst ke baad woh turant re-request karta hai aur phir se jeet jaata hai. Network aur Audio ko kabhi grant nahi milta → unka wait time unbounded (infinite) ho jaata hai. Audio starve ho jaata hai. Round-robin: jab koi master bus use kar leta hai, uski priority $(i + 1) mod N$ ke through bottom mein chali jaati hai. Toh grant order ban jaata hai Disk → Network → Audio → Disk → … Har master zyada se zyada baaki do bursts wait karta hai. $N = 3$ masters aur $1000$ -cycle bursts ke saath, Audio ka worst-case wait hai $2 \times 1000 = 2000 cycles,$ aur use har $3000$ cycles mein ek baar bus guarantee hai. Uska bus share $\frac{1}{3} \approx 33.3%$ hai, finite aur fair.

Level 4 — Synthesis

Exercise 4.1 (L4)

Tumhe ek SSD se sustained 3.0 GB/s par RAM mein stream karna hai 64-bit (8-byte) bus par. DMA burst ya cycle-stealing run kar sakta hai; cycle-stealing mein $T_{arb} = 3$ , $T_{transfer} = 1$ per transfer hai; burst mein $T_{cycle} = 1$ aur negligible setup hai. Minimum bus frequency $f_{bus}$ nikalo jo har mode ke liye zaroori hai keep up karne ke liye. Kaunsa mode $500 MHz$ bus par feasible hai?

Recall Solution

Required transfer rate transfers/s mein (8 bytes each): $R = \frac{3.0 \times 1 0 ^{9} B/s}{8 B} = 3.75 \times 1 0^{8} transfers/s .$ Burst: $1$ cycle per transfer, toh $\geq 3.75 \times 1 0^{8}$ cycles/s chahiye: $f_{burst} \geq 375 MHz .$ Cycle-stealing: $T_{arb} + T_{transfer} = 4$ cycles per transfer: $f_{steal} \geq 4 \times 3.75 \times 1 0^{8} = 1.5 \times 1 0^{9} = 1500 MHz = 1.5 GHz .$ $500 MHz$ bus par: burst ko $375 MHz$ chahiye ✓ (feasible, headroom ke saath), cycle-stealing ko $1.5 GHz$ chahiye ✗ (impossible). Burst mode use karo.

Exercise 4.2 (L4)

Usi 3 GB/s burst stream par ( $500 MHz$ bus par feasible), ek burst bus ko 1024 transfers ke liye hold karta hai. Har burst ke dauran CPU fully blocked rehta hai. Agar CPU ko bhi bus chahiye aur woh zyada se zyada 2 µs blocking tolerate kar sakta hai, toh kya ek single burst yeh violate karta hai? Agar haan, toh maximum burst length kya hai jo blocking ko $2 μ s$ ke andar rakhti hai?

Recall Solution

$500 MHz$ par, ek cycle $= 2 ns$ . Ek $1024$ -transfer burst (1 cycle each) $= 1024 \times 2 ns = 2048 ns = 2.048 μ s$ . Yeh $2 μ s$ exceed karta hai — CPU bahut zyada der block ho jaata hai. $2 μ s$ ke andar max transfers: $\frac{2000 ns}{2 ns} = 1000$ transfers. Toh burst length $\leq 1000$ transfers set karo (parent ka CSR burst field 0–255 hold karta hai, toh practically tum $\leq 255$ ke bursts program karoge aur engine unhe chain karne do). Jaise $256$ -transfer bursts program karo toh sirf $256 \times 2 ns = 512 ns$ block hota hai, limit se comfortably under.

Level 5 — Mastery

Exercise 5.1 (L5)

Design decision. Ek system mein hai: (a) ek real-time UART UART receiver jo har $10 μ s$ mein 1 byte drip karta hai aur koi byte lose nahi kar sakta, aur (b) ek bulk PCIe PCIe transfer of $16 MB$ jo maximum throughput chahta hai. Bus $250 MHz$ , 32-bit hai. Har DMA channel ke liye ek transfer mode choose karo, numbers se justify karo, aur priority scheme batao. Interrupts aur Cache Coherency ke saath interaction ko consider karo.

Recall Solution

UART channel → cycle-stealing (ya single-transfer). Use sirf har $10 μ s$ mein $1$ byte chahiye — yeh $1 0^{5}$ B/s ka rate hai, jo per-transfer arbitration ke saath bhi trivially meet ho jaata hai ( $4$ cycles $= 16 ns$ per byte $250 MHz$ bus par). Jo yeh tolerate nahi kar sakta woh hai latency: agar ek lamba burst bus hold kare, toh UART ka 1-byte FIFO overflow ho jaata hai aur ek byte lost ho jaata hai. Cycle-stealing har transfer ke baad bus release kar deta hai, UART ko prompt service guarantee karta hai.

PCIe channel → burst mode. $16 MB = 16, 777, 216$ bytes, $\div 4 = 4, 194, 304$ transfers. Burst mein $1$ cycle each par, $4 ns$ /cycle → $4, 194, 304 \times 4 ns \approx 16.78 ms$ . Cycle-stealing ( $4$ cycles) mein $\approx 67 ms$ lagta — 4× bura. Bulk data burst chahta hai.

Priority: UART ko higher priority do (fixed priority UART > PCIe) taaki uski rare, latency-critical requests bulk bursts ko preempt kar sakein. Kyunki UART sirf har $10 μ s$ mein request karta hai aur bus $\sim 16 ns$ hold karta hai, yeh bus time ka negligible $0.16%$ steal karta hai — PCIe ko hardly pata chalta hai. Lekin PCIe burst length limit karo (Ex 4.2 logic) taaki woh itni baar check in kare ki ek UART request kabhi ek chhote burst se zyada wait na kare.

Interrupts: PCIe channel $CSR.IE = 1$ set karta hai taaki 16 MB block complete hone par ek interrupt raise ho (har byte par nahi) — yahi DMA ka programmed I/O ke upar point hai. UART channel per-buffer completion interrupts use kar sakta hai.

Cache coherency: DMA RAM mein likhta hai CPU ke cache ke peeche. PCIe DMA finish hone ke baad, CPU ka un addresses ka cached copy stale ho jaata hai. Ya toh interconnect snoop/invalidate kare (hardware coherency, cf. ARM AMBA AXI ACE) ya driver ko DMA'd data padhne se pehle cache range invalidate karna hoga. Yeh skip karo toh CPU purana garbage padhega.

Recall Numeric summary

UART rate need: $1 0^{5}$ B/s; per-byte cost $16 ns$ ⇒ effortless.
PCIe burst time: $\approx 16.78 ms$ ; cycle-steal: $\approx 67.1 ms$ (4×).
UART bus occupancy at 1 byte/ $10 μ s$ : $\frac{16 ns}{10000 ns} = 0.16%$ .

Recall Self-check ladder

Kaun sa timing formula per-transfer arbitration built in rakhta hai? ::: Cycle-stealing, $T_{steal} = N (T_{arb} + T_{transfer})$ . Tum ek byte rate ko bus frequency demand mein kaise convert karte ho? ::: Width se divide karo transfers/s paane ke liye, cycles-per-transfer se multiply karo, woh cycles/s count hi minimum frequency hai. Saturation mein, fixed priority low-priority masters ko kyun starve karta hai jabki round-robin nahi karta? ::: Round-robin ek served master ko bottom mein drop kar deta hai, har master ka wait baaki $N - 1$ bursts tak bound kar deta hai; fixed priority ek continuously-requesting top master ko hamesha jeetnay deta hai. Ek DMA write to RAM ke baad, CPU galat data kyun padh sakta hai? ::: Uska cache abhi bhi stale pre-DMA value hold karta hai; range invalidate karni padegi ya interconnect ko snoop karna hoga.

Related: Bus Architecture · Memory-Mapped IO · SDRAM Controllers · DMA controllers