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5.2.4 · D5 · HinglishProcessor Datapath & Pipelining

Question bank — Pipeline registers and control signals

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5.2.4 · D5 · Hardware › Processor Datapath & Pipelining › Pipeline registers and control signals

Shuru karne se pehle, teen vocabulary anchors jinpar hum baar baar lean karte hain.

Stage — 5-worker assembly line mein ek worker: Fetch → Decode → Execute → Memory → Write-back (short: IF, ID, EX, MEM, WB).

Pipeline register — woh tray (edge-triggered flip-flops ka ek bank — dekho Clocking and edge-triggered flip-flops) jo do workers ke beech baithti hai, clock edge par sab kuch latch karti hai. "Latch" = "abhi value freeze karo taaki next worker use next cycle mein padhe." Exactly chaar hote hain, har ek ka naam un do stages ke naam par hai jinhe woh straddle karta hai:

Register Kis ke beech baitha hai Picture mein dekho
IF/ID Fetch → Decode pehli tray
ID/EX Decode → Execute doosri tray
EX/MEM Execute → Memory teesri tray
MEM/WB Memory → Write-back chauthi tray

Control bundle — control unit (ID mein) kai saari 1-bit "sticky notes" produce karta hai (RegWrite, MemRead, ALUSrc, …). Hum inhe group karte hain us stage ke hisaab se jo finally inhe use karta hai, aur har group ko bundle kehte hain:

  • EX bundle — ALUSrc, ALUOp, RegDst (Execute mein use hota hai)
  • MEM bundle — MemRead, MemWrite, Branch (Memory mein use hota hai)
  • WB bundle — RegWrite, MemtoReg (Write-back mein use hota hai)

Neeche ki picture mein chaaon saari trays hain, aur dikhaya hai ki teen bundles ek ek karke kaise drop hoti hain jab ek instruction right ki taraf badhta hai. Jab bhi koi naam neeche unfamiliar lage to ise refer karo.

Figure — Pipeline registers and control signals

True or false — justify

Har pipeline register exactly same set of fields store karta hai.
False — har register sirf wahi carry karta hai jo baad ke stages ko abhi bhi chahiye; e.g. MEM/WB ab store data ya branch target carry nahi karta kyunki woh pehle hi consume ho chuke hain, isliye woh EX/MEM se narrower hota hai.
Write-back stage ke baad ek pipeline register hota hai.
False — WB register file mein likhta hai, jo already stateful storage hai, isliye extra latch sirf write ko ek cycle delay karega aur hazards badha dega. Sirf chaar registers exist karte hain.
Control signals har stage mein independently generate hote hain us stage ki local logic se.
False — sirf Decode hi opcode dekhta hai, isliye saare control signals ek baar ID mein generate hote hain aur phir forward carry kiye jaate hain; baad ke stages inhe re-derive nahi kar sakte.
RegWrite signal usi cycle mein use hota hai jis mein generate hota hai.
False — yeh ID mein generate hota hai lekin sirf WB mein consume hota hai, teen cycles baad, isliye ise ID/EX → EX/MEM → MEM/WB ride karna padta hai kuch kaam karne se pehle.
Ek pipeline register jo control signal carry karta hai, woh signal consuming stage ke baad drop kar deta hai.
True — EX bundle, EX ke baad drop hota hai, MEM bundle, MEM ke baad, isliye har successive register pehle wale se kam control bits hold karta hai.
Destination register number sirf Decode stage mein chahiye jahan se instruction se padha jaata hai.
False — yeh ID mein padha jaata hai lekin WB mein use hota hai yeh decide karne ke liye ki kis register mein likhna hai, isliye 5-bit number ko saare registers ke through travel karna padta hai warna WB galat jagah likhega.
Ek pipeline register ko extra fields se widening karna jo koi baad ka stage nahi padhe, sirf wasteful hai, harmful nahi.
Correctness par roughly true lekin discipline par false — extra flip-flops area aur power jalate hain aur ek design misunderstanding signal karte hain; ek register ki width un fields ke sum ke barabar honi chahiye jo baad ke stage ko physically chahiye, kuch zyada nahi.
PC+4 ko Fetch stage khatam hone ke baad discard kiya ja sakta hai.
False — branch target (neeche define kiya gaya hai) Execute mein compute hota hai, isliye PC+4 ko ID/EX ke through survive karna padta hai EX adder tak pahunchne ke liye.

Spot the error

"Stage 5 (WB) opcode inspect karta hai yeh decide karne ke liye ki register file mein likhna hai ya nahi."
Opcode WB tak aate aate kabka ja chuka hota hai — instruction word sirf IF/ID mein rehta hai. WB MEM/WB mein carry kiya hua latched RegWrite bit padhta hai iske bajaye.
"Kyunki EX RegWrite use nahi karta, hum ise EX/MEM par safely drop kar sakte hain."
Galat — EX ise consume nahi karta, lekin WB (ek baad ka stage) abhi bhi ise chahiye, isliye EX ko ise unchanged EX/MEM mein copy forward karna padta hai. Sirf woh signals drop hote hain jinke consuming stage nikal chuki ho.
"Write-back us register mein likhta hai jo abhi IF/ID mein current instruction mein named hai."
Pipeline mein paanch alag alag instructions paanch stages occupy karte hain; IF/ID instruction WB mein wale se chaar cycles baad fetch hua tha. WB ko woh dest # use karna chahiye jo uske apne (purane) instruction ke saath travel kiya ho.
"Hum Memory stage mein current instruction ke immediate se branch target recompute karte hain."
Immediate us instruction ka hoga jo abhi MEM mein hai, zaruri nahi ki woh branch ho. Target EX mein compute hota hai aur EX/MEM mein latched hota hai; MEM sirf stored target padhta hai.
"EX/MEM register mein sign-extended immediate carry karna chahiye taaki MEM ise use kar sake."
MEM raw immediate use nahi karta — immediate EX mein already ALU/branch adder dwara consume ho chuka tha. EX/MEM jo carry karta hai woh hai ALU result aur branch target, us immediate ko use karne ke products.
"Kyunki pipeline mein 5 stages hain, symmetry ke liye 5 pipeline registers chahiye."
Registers stages ke beech baithte hain, isliye 5 stages ke 4 gaps hote hain. Last stage ka output register file mein jaata hai, kisi aur tray mein nahi.
"MEM stage ke liye control signals MEM stage mein generate karne chahiye taaki woh fresh rahein."
MEM opcode nahi dekh sakta, isliye inhe generate karne ka uske paas koi tarika nahi; woh ek baar ID mein decode hote hain aur MEM bundle mein ID/EX → EX/MEM ke through carry kiye jaate hain.

Why questions

Hum simply opcode ko har stage mein re-decode kyun nahi kar sakte control signals carry karne ki jagah?
Kyunki ID ke baad opcode available nahi rehta — pipeline registers data aur latched signals carry karte hain, poora instruction word nahi — isliye Decode ke baad re-decoding physically impossible hai.
Control signals ko EX, MEM, aur WB bundles mein kyun split kiya jaata hai ek lump ki jagah?
Consuming stage ke hisaab se grouping karne se har register apna poora bundle drop kar sakta hai jaise hi uski stage khatam hoti hai, width minimize hoti hai aur yeh obvious ho jaata hai ki har signal kahan use hota hai.
Har woh value jo baad ka stage chahiye use kyun latch karna padta hai, chahe current stage use ignore kare?
Producing stage next cycle ek naye instruction par move kar jaata hai aur apne combinational outputs overwrite kar deta hai; jo kuch latch nahi kiya gaya woh lost ho jaata hai, isliye unused-but-needed values copy through ki jaati hain.
Forwarding (dekho Forwarding and stalling) apne operands pipeline registers se kyun padhta hai register file se nahi?
Kyunki sabse naya correct value EX/MEM ya MEM/WB mein rehta hai write back hone se pehle — register file abhi bhi stale value hold karti hai, isliye forwarding directly registers tap karta hai.
ALU ka Zero flag EX/MEM mein kyun latched hota hai?
Agar branch MEM stage mein resolve hota hai, to MEM ko comparison outcome chahiye; flag EX mein produce hota hai aur jab EX ek naya instruction leta hai to woh gayab ho jaata, isliye ise carry karna padta hai.
Control signals ko pipeline registers ke andar rakhne se automatically har instruction ka paperwork apne saath kyun rehta hai?
Har instruction har register mein ek slot occupy karta hai jaisa woh advance karta hai, isliye uske signals uske data ke saath lockstep mein march karte hain — paanch in-flight instructions ke beech koi cross-talk nahi.

Edge cases

Ek nop (no-operation) ke liye, travel karte waqt control bundles mein kya hona chahiye?
Saare state-changing signals — RegWrite, MemWrite — 0 hone chahiye taaki nop kuch na likhe; bits phir bhi registers mein ride karte hain, bas woh ek "do nothing" instruction carry karte hain.
Jab hazard ek stall force karta hai, to ID/EX control field mein kya inject kiya jaata hai?
Ek bubble — control bundle zero kiya jaata hai (RegWrite=0, MemWrite=0) taaki stalled slot ek nop ki tarah behave kare aur koi state commit na kare, jabki earlier stages apni values hold karti hain (dekho Pipeline hazards).
Jab ek branch mispredicted hoti hai, to IF/ID aur ID/EX mein already existing wrong-path instructions ka kya hona chahiye?
Unhe flush (squash) kiya jaata hai — unhe hold karne wale pipeline registers ke control bundles zero kiye jaate hain, in-flight instructions ko bubbles mein badal dete hain taaki unke RegWrite/MemWrite kabhi fire na karein aur koi wrong-path state commit na ho (yeh ek control hazard hai, dekho Pipeline hazards).
Flush sirf control fields kyun zero karta hai lekin data fields clear karne ki taklif kyun nahi karta?
Kyunki harmless data active write signal ke bina kuch nahi karta — agar RegWrite=MemWrite=0 hai, to data fields mein jo bhi garbage baitha hai woh kabhi kahi nahi likha jaata, isliye sirf control bits squash karne zaroori hain.
Ek R-type instruction ka koi memory access nahi hota — kya woh phir bhi MEM-bundle signals carry karta hai?
Haan, woh carry karta hai lekin MemRead=MemWrite=0 ke saath; fields har instruction ke liye exist karte hain, aur ek non-memory op unhe omit karne ki jagah simply inactive set karta hai.
Ek sw (store) koi register nahi likhta — kya uska dest-reg # field phir bhi latched hota hai?
5-bit field phir bhi travel karta hai (datapath uniform hai), lekin uska WB bundle RegWrite=0 set karta hai, isliye jo bhi number wahan baitha ho woh harmlessly ignore ho jaata hai.
Reset ke baad pehle clock edges par, pipeline registers undefined values hold karte hain — yeh sirf ek properly reset design mein safe kyun hai?
Yeh safe hai sirf tab jab control bundles hold karne wale flip-flops mein ek synchronous ya asynchronous reset ho jo power-up par RegWrite=MemWrite=0 force kare; aise resettable flops ke bina garbage control bits spurious writes trigger kar sakti hain, isliye real designs control registers ko explicit reset dete hain chahe data fields ka koi reset na ho.
Agar do instructions ko same cycle mein same physical pipeline register slot chahiye, to kya galat hua?
Kuch galat ho hi nahi sakta — har register by construction ek instruction ke fields ek cycle mein hold karta hai; agar ek design kabhi do maangta, to iska matlab hai ek stage skip kiya gaya ya clocking mis-timed thi (dekho Clocking and edge-triggered flip-flops).

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