Multi-cycle datapath: Foundations — Hinglish deep dive

5.2.2 · D1 · Hardware › Processor Datapath & Pipelining › Multi-cycle datapath

Multi-cycle datapath page padhne se pehle, tumhe woh har word aur symbol apna banana hoga jo woh tumhare saamne phenkta hai. Yeh page unhe ek-ek karke, bilkul zero se build karta hai. Koi bhi box, arrow, ya symbol yahan tab tak nahi aata jab tak hum use draw na kar lein.

0. "Datapath" aakhir hai kya?

Figure dekho. Har rectangle ek aisi box hai jo bits ko hold ya transform karti hai. Har arrow wires ka ek bundle hai jo ek number ko ek box se dusre mein le jaata hai. Puri page is baare mein hai ki har arrow ko value carry karne ki permission kab milti hai — woh "kab" clock hai.

Topic ko yeh kyun chahiye? Kyunki "multi-cycle" ka matlab hai is plumbing mein safar ko timed legs mein todna. Jab tak tum pipes nahi dekhte, legs samajh nahi aate.

Prerequisite: yeh wahi boxes ka set hai jo tumne Single-cycle datapath mein dekha tha — multi-cycle bas tumhe unhe time ke across reuse karne deta hai.

1. Bits, ek word, aur register — memory box

Parent note ke internal registers — IR, A, B, ALUOut, MDR — sab usi ek box ke example hain, har ek alag value pakadta hai:

Register	Sticky note jo woh rakhta hai	Kis step mein pakdi
IR	instruction bits khud	IF
A, B	register file se padhi do values	ID
ALUOut	ALU ka latest result	ID / EX
MDR	Memory Data Register — memory se padha ek word	MEM

2. Clock aur "cycle"

Square wave dekho. Ek cycle = ek pura period, ek rising edge se dusre tak. Ek signal ko apni box se travel karna next edge se pehle khatam ho jaana chahiye, warna register garbage pakad leta hai. Isliye $T$ kabhi bhi us cheez se chhota nahi ho sakta jo ek cycle mein honi chahiye:

Yeh ek inequality hi multi-cycle ke hone ki poori wajah hai.

3. Symbols $\leftarrow$ , $[]$ , aur $[a : b]$ padhna

Parent note aise lines likhta hai jaise $IR \leftarrow Memory [PC]$ . Usme teen symbols chhupe hain.

Topic ko yeh kyun chahiye: parent mein har step ek ya do aise copy-lines ke roop mein likha hai. Jab ek baar tum $\leftarrow$ aur $[]$ padh lo, toh poora "five steps" table bilkul seedha English hai.

4. PC, IR, ALU, register file, memory — naami boxes

5. Delay, aur "worst-case"

Topic ko yeh kyun chahiye: parent ka Example 1 poora "sabse lambe path par delays jodo" ke baare mein hai. ID step ke liye 300 ps ka number ek register read (100) se aata hai jo ussi cycle mein turant ek ALU op (200) ke baad hoti hai — 100 + 200 = 300.

6. CPI — cycles ko ek single fairness number mein badalna

Plain average ki jagah weighted average kyun? Kyunki ek rare 5-cycle lw ko ek common 4-cycle add se kam count karna chahiye. Har cycle count ko uski frequency se multiply karna exactly yehi karta hai. Yeh seedha CPI and CPU performance equation mein jaata hai.

Yeh foundations topic ko kaise feed karte hain

Left par sab kuch is page par define hai; right par ek node parent topic hai. Agar koi left-node shaky lage, uska section upar dobara padho.

Equipment checklist

Sawaal padho, apne dimag mein jawab socho, phir reveal karo.

x \leftarrow y

ka kya matlab hai, aur yeh

x = y

se alag kaise hai?

"Clock edge par

y

ko box

x

mein copy karo" — ek one-way action, equality ka statement nahi.

Memory [PC]

kya pick karta hai?

Woh word jo PC register mein currently stored address par rakha hai.

IR [25 : 21]

ka kya matlab hai?

Instruction word ke bits 25 se 21 tak (paanch bits) — register number ke roop mein use hote hain.

Clock period

T

arbitrarily chhota kyun nahi ho sakta?

Ek signal ko next clock edge se pehle apni box se travel karna khatam karna chahiye, isliye

T \geq

ek cycle mein kiye jaane wale sabse slow kaam se.

Ek register (sticky note) multi-cycle ko possible kyun banata hai?

Combinational boxes apna output kho dete hain jab inputs badlte hain; ek register result ko pakadta aur hold karta hai taaki baad ka cycle use padh sake.

Paanch internal registers aur woh kya hold karte hain naam batao.

IR (instruction bits), A aur B (do register-file values), ALUOut (latest ALU result), MDR (memory se padha ek word).

Ek ALU poori instruction ko serve kyun kar sakta hai?

PC+4, branch target, aur real arithmetic alag cycles mein hote hain, toh wahi ALU unke across reuse hota hai.

CPI ka kya matlab hai aur isko kaise compute karte hain?

Cycles Per Instruction — har type ke cycle count ka frequency-weighted average

\sum_{i} f_{i} c_{i}

CPI ek weighted average kyun hai?

Taaki common instructions average ko rare ones se zyada influence karein.