Intuition The One Core IdeaRISC-V is a menu, not a fixed meal : a tiny mandatory "base" of instructions, plus optional bolt-on extensions (M, A, F, D, V, C) that each add one family of powers — multiply, atomics, floats, doubles, vectors, compression. Everything on the parent page is just reading that menu , so before you can order you must know what a "bit", a "register", a "word", "two's complement", "signed vs unsigned", and "IEEE 754" actually mean — this page builds every one of those from nothing.
This page assumes you have seen none of the notation on the parent page. We earn every symbol before it appears. Start at line one.
A bit is a single box that holds exactly one of two things: 0 or 1. That's all. Nothing smaller exists in a computer.
A wire is either carrying voltage (call it 1) or not (0). Two clean states are easy to build and hard to confuse. Every number, letter, float, and instruction on the parent page is ultimately a row of these boxes .
When we line up many boxes we count positions from the right, starting at 0 . The rightmost box is position 0, the next is position 1, and so on. That position number is called the bit index .
Definition Bit index and the notation[hi:lo]
[31:0] means "boxes number 31 down to number 0" — i.e. all 32 boxes. [63:32] means "boxes 63 down to 32" — the upper half of a 64-box row. The parent page writes exactly this when it says MUL takes bits [31:0] and MULH takes [63:32].
Each box has a weight . Position i 2 i 1.
Worked example Reading a rowBoxes (index 3,2,1,0) = 1011.
Value = 1 ⋅ 2 3 + 0 ⋅ 2 2 + 1 ⋅ 2 1 + 1 ⋅ 2 0 = 8 + 0 + 2 + 1 = 11
Definition Word / register widthA register is a fixed-size row of bits inside the CPU that it can read and write in one step. Its length is the word width . RISC-V comes in a 32-bit flavour (row of 32 boxes) and a 64-bit flavour (row of 64 boxes).
That is what the 32 and 64 mean in RV32I and RV64I:
RV = RISC-V.32 or 64 = how many boxes per register.I = the Integer base — the mandatory core the 5.1.07-RISC-V-base-ISA defines.
rd, rs1, rs2
Instructions name registers by role, not by number:
rs1 = read source 1 (first input register).rs2 = read source 2 (second input register).rd = destination (where the answer is written).
So MUL rd, rs1, rs2 reads two registers, multiplies, and writes the result into a third. Names like t0, t1, a0, a1 are just specific registers filling those roles.
Writing 32 boxes is exhausting. We group them 4 boxes at a time , because 4 bits have 2 4 = 16 0–9 then A–F. This is hexadecimal ("base 16"), written with a leading 0x.
So 0x80000000 is 1000 then seven 0000 groups = a 1 in the leftmost box of 32, everything else 0. Keep that picture — it is the star of the parent page's tricky multiply example.
The same row of boxes can be read two ways.
Unsigned reading: every box is a positive weight, exactly like §1. A 32-bit row ranges 0 … 2 32 − 1
Definition Signed (two's complement)Signed reading gives the leftmost box a negative weight . In 32 bits its weight is − 2 31 + 2 31
0x80000000 is − 2 31 0x80000000 = only the top box is 1. Unsigned it means + 2 31 = 2 , 147 , 483 , 648 Signed it means − 2 31 = − 2 , 147 , 483 , 648 MULH (signed) and MULHU (unsigned) can give different answers.
Common mistake Thinking there is "the" value of a rowWrong idea: a bit pattern has one number.
Fix: a pattern has a number only once you choose signed or unsigned . That choice is why RISC-V needs both DIV/DIVU, MULH/MULHU, and the mixed MULHSU. The letter U on an instruction always means "read the boxes as unsigned."
Multiply two 32-box numbers and the answer may need up to 64 boxes . A single 32-bit register cannot hold it, so the hardware splits the result:
That single fact explains the whole "why two results?" section on the parent page — nothing more mysterious than long multiplication overflowing its column.
Integers can't store 1.75. The F and D extensions read a register as a floating-point number using the 5.2.03-IEEE-754-floating-point layout. The bits are cut into three fields:
Definition The three fields
sign (1 box): 0 = positive, 1 = negative.exponent (8 boxes for single, 11 for double): says how far to slide the binary point .mantissa (23 boxes for single, 52 for double): the fraction digits after an assumed leading 1.
Common mistake "Floats store any decimal exactly"Wrong idea: the fraction is exact.
Fix: the mantissa is a finite pile of 2 − k 1.5 = 1 + 0.5 and 0.25 fit exactly, but 0.1 needs an endless repeating pattern — chopped to 23 bits it is slightly off. That's why the parent page warns (0.1 + 0.2) == 0.3 is false.
The A extension talks about many CPUs sharing memory. Three plain-word terms:
Definition Core, atomic, cache line
A core is one independent CPU that runs its own instruction stream.
Atomic means "all-or-nothing": a read-modify-write that no other core can interrupt halfway.A cache line is the fixed-size chunk of memory that hardware tracks ownership of; the 6.4.02-Cache-coherence-protocols machinery watches these chunks, and LR/SC piggyback on that watching.
Definition Vector vs scalar, compressed
A scalar operation touches one number; a vector operation applies the same op to a whole row of numbers at once — the idea behind 7.1.05-SIMD-and-vector-processors that the V extension exposes.
Compressed (C) instructions are the same operations packed into 16 boxes instead of 32, to save program size — an 3.3.06-Instruction-encoding trick, not a new capability.
place value powers of two
M extension multiply and divide
instruction encoding size
What is a bit and why exactly two states? One box holding 0 or 1; two states map cleanly to "voltage / no voltage."
What does place value 2 i The box at index i 2 i 1 boxes.
What do [31:0] and [63:32] select? The low 32 boxes, and the upper 32 boxes, of a 64-box row.
Decode RV64I. RISC-V, 64-bit registers, the mandatory Integer base.
What roles do rd, rs1, rs2 play? Destination register, read-source 1, read-source 2.
One hex digit equals how many bits? Four bits (2 4 = 16
What is 0x80000000 unsigned vs signed? + 2 31 − 2 31
Why does the top box flip sign in two's complement? Its weight becomes − 2 31 + 2 31
Why does a 32×32 multiply need 64 bits? The product can be as large as needs 64 boxes; hardware splits it into upper (MULH) and lower (MUL).
Name the three IEEE 754 fields. Sign, exponent, mantissa.
Why subtract 127 from the exponent? It is the bias; storing the exponent unsigned lets simple comparators sort floats, and subtracting recovers the true exponent.
Why is 0.1 not exact in a float? Its binary fraction repeats forever; truncating to 23 bits leaves a small error.
Define atomic and cache line. Atomic = uninterruptible all-or-nothing; cache line = the memory chunk hardware tracks for coherence.
Scalar vs vector? Scalar = one number per op; vector = same op on a whole row of numbers at once.
