5.1.8 · D1RISC-V extensions (M, A, F, D, V, C)
RISC-V ek menu hai, fixed meal nahi : instructions ka ek chhota sa mandatory "base", plus optional bolt-on extensions (M, A, F, D, V, C) jo har ek alag family of powers add karte hain — multiply, atomics, floats, doubles, vectors, compression. Parent page par jo bhi hai woh sirf us menu ko padhna hai, toh order karne se pehle tumhe ye jaanna zaroori hai ki "bit", "register", "word", "two's complement", "signed vs unsigned", aur "IEEE 754" actually matlab kya rakhte hain — yeh page un sab ko zero se build karta hai.
Yeh page assume karta hai ki tumne parent page par koi bhi notation pehle nahi dekha. Hum har symbol ko earn karte hain pehle use karne se. Line one se shuru karo.
Ek bit ek single box hai jo sirf do chezon mein se ek hold karta hai: 0 ya 1. Bas itna hi. Computer mein isse chhoti koi cheez exist nahi karti.
Ek wire ya toh voltage carry kar rahi hoti hai (use 1 kaho) ya nahi kar rahi (0). Do clean states banane mein aasaan aur confuse hone mein mushkil hote hain. Parent page par har number, letter, float, aur instruction ultimately in boxes ki ek row hai.
Jab hum bahut saare boxes line up karte hain toh positions ko right se count karte hain, 0 se shuru karke . Sabse rightmost box position 0 hai, agla position 1 hai, aur aage bhi aise hi. Woh position number bit index kehlata hai.
Definition Bit index aur notation[hi:lo]
[31:0] matlab hai "boxes number 31 se lekar number 0 tak" — yaani saare 32 boxes. [63:32] matlab hai "boxes 63 se 32 tak" — 64-box row ka upper half. Parent page exactly yahi likhta hai jab woh kehta hai MUL bits [31:0] leta hai aur MULH [63:32] leta hai.
Har box ki ek weight hoti hai. Position i 2 i 1 hold karti hain.
Worked example Ek row padhnaBoxes (index 3,2,1,0) = 1011.
Value = 1 ⋅ 2 3 + 0 ⋅ 2 2 + 1 ⋅ 2 1 + 1 ⋅ 2 0 = 8 + 0 + 2 + 1 = 11
Definition Word / register widthEk register CPU ke andar bits ki ek fixed-size row hoti hai jise woh ek step mein read aur write kar sakta hai. Uski length word width kehlati hai. RISC-V 32-bit flavour (32 boxes ki row) aur 64-bit flavour (64 boxes ki row) mein aata hai.
Yahi woh 32 aur 64 hain jo RV32I aur RV64I mein hain:
RV = RISC-V.32 ya 64 = har register mein kitne boxes hain.I = Integer base — woh mandatory core jo 5.1.07-RISC-V-base-ISA define karta hai.
rd, rs1, rs2
Instructions registers ko number se nahi, role se name karti hain:
rs1 = read source 1 (pehla input register).rs2 = read source 2 (doosra input register).rd = destination (jahan answer likha jata hai).
Toh MUL rd, rs1, rs2 do registers padhta hai, multiply karta hai, aur result ek teesre mein likhta hai. t0, t1, a0, a1 jaise names sirf specific registers hain jo un roles ko fill karte hain.
32 boxes likhna thaka dene wala hai. Hum unhe 4 boxes at a time group karte hain, kyunki 4 bits ke 2 4 = 16 0–9 phir A–F dete hain. Yeh hexadecimal ("base 16") kehlata hai, leading 0x ke saath likha jata hai.
Toh 0x80000000 hai 1000 phir saat 0000 groups = 32 ke leftmost box mein ek 1, baaki sab 0. Yeh picture yaad rakho — yeh parent page ke tricky multiply example ka star hai.
Boxes ki same row ko do tarakon se padha ja sakta hai.
Unsigned reading: har box ek positive weight hai, exactly §1 ki tarah. 32-bit row ka range hota hai 0 … 2 32 − 1
Definition Signed (two's complement)Signed reading leftmost box ko ek negative weight deta hai . 32 bits mein uski weight − 2 31 + 2 31
0x80000000 hai − 2 31 0x80000000 = sirf top box 1 hai. Unsigned iska matlab hai + 2 31 = 2 , 147 , 483 , 648 Signed iska matlab hai − 2 31 = − 2 , 147 , 483 , 648 MULH (signed) aur MULHU (unsigned) alag answers de sakte hain.
Common mistake Yeh sochna ki ek row ki "the" value hoti haiGalat idea: ek bit pattern ka ek number hota hai.
Fix: ek pattern ka ek number hota hai sirf tab jab tum signed ya unsigned choose karo . Yahi choice reason hai kyun RISC-V ko DIV/DIVU, MULH/MULHU, aur mixed MULHSU dono chahiye. Kisi instruction par letter U ka matlab hamesha hai "boxes ko unsigned padho."
Do 32-box numbers multiply karo aur answer ko 64 boxes tak ki zaroorat pad sakti hai. Ek single 32-bit register isse hold nahi kar sakta, toh hardware result ko split karta hai:
Yeh single fact parent page ke poore "why two results?" section ko explain karta hai — long multiplication ke apne column overflow karne se zyada kuch mysterious nahi hai.
Integers 1.75 store nahi kar sakte. F aur D extensions ek register ko 5.2.03-IEEE-754-floating-point layout use karke floating-point number ki tarah padhte hain. Bits ko teen fields mein cut kiya jata hai:
sign (1 box): 0 = positive, 1 = negative.exponent (single ke liye 8 boxes, double ke liye 11): kehta hai binary point ko kitna door slide karna hai .mantissa (single ke liye 23 boxes, double ke liye 52): ek assumed leading 1 ke baad ke fraction digits.
Common mistake "Floats koi bhi decimal exactly store karte hain"Galat idea: fraction exact hai.
Fix: mantissa 2 − k finite pile hai. 1.5 = 1 + 0.5 aur 0.25 exactly fit hote hain, lekin 0.1 ko ek endless repeating pattern chahiye — 23 bits par chop karne par yeh thoda off ho jata hai. Yahi reason hai kyun parent page warn karta hai ki (0.1 + 0.2) == 0.3 false hai.
A extension bahut saare CPUs ke memory share karne ke baare mein baat karta hai. Teen plain-word terms:
Definition Core, atomic, cache line
Ek core ek independent CPU hai jo apna khud ka instruction stream run karta hai.
Atomic ka matlab hai "all-or-nothing": ek read-modify-write jise koi doosra core beech mein interrupt nahi kar sakta.Ek cache line memory ka fixed-size chunk hai jiska ownership hardware track karta hai; 6.4.02-Cache-coherence-protocols machinery in chunks ko dekhti rehti hai, aur LR/SC us watching par piggyback karte hain.
Definition Vector vs scalar, compressed
Ek scalar operation ek number ko touch karta hai; ek vector operation same op ko ek saath numbers ki puri row par apply karta hai — yeh 7.1.05-SIMD-and-vector-processors ke peeche ka idea hai jo V extension expose karta hai.
Compressed (C) instructions wahi same operations hain jo 32 ki jagah 16 boxes mein pack ki hain, program size bachane ke liye — ek 3.3.06-Instruction-encoding trick hai, koi naya capability nahi.
place value powers of two
M extension multiply and divide
instruction encoding size
Bit kya hota hai aur exactly do states kyun? Ek box jo 0 ya 1 hold karta hai; do states cleanly "voltage / no voltage" se map hoti hain.
Place value 2 i Index i 2 i 1 boxes ki weights add karo.
[31:0] aur [63:32] kya select karte hain?Low 32 boxes, aur 64-box row ke upper 32 boxes.
RV64I decode karo.RISC-V, 64-bit registers, mandatory Integer base.
rd, rs1, rs2 kya roles play karte hain?Destination register, read-source 1, read-source 2.
Ek hex digit kitne bits ke barabar hai? Chaar bits (2 4 = 16
0x80000000 unsigned vs signed kya hai?+ 2 31 − 2 31
Two's complement mein top box sign kyun flip karta hai? Uski weight + 2 31 − 2 31
32×32 multiply ko 64 bits kyun chahiye? Product itna bada ho sakta hai ki 64 boxes chahiye; hardware isse upper (MULH) aur lower (MUL) mein split karta hai.
IEEE 754 ke teen fields ke naam batao. Sign, exponent, mantissa.
Exponent se 127 kyun subtract karte hain? Yeh bias hai; exponent ko unsigned store karne se simple comparators floats sort kar sakte hain, aur subtract karne se true exponent recover hota hai.
0.1 ek float mein exact kyun nahi hota?Uska binary fraction forever repeat karta hai; 23 bits par truncate karne par ek chhoti si error reh jaati hai.
Atomic aur cache line define karo. Atomic = uninterruptible all-or-nothing; cache line = woh memory chunk jise hardware coherence ke liye track karta hai.
Scalar vs vector? Scalar = ek op par ek number; vector = ek saath numbers ki puri row par same op.
