5.1.3 · D4 · HinglishInstruction Set Architecture (ISA)

ExercisesAddressing modes

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5.1.3 · D4 · Hardware › Instruction Set Architecture (ISA) › Addressing modes

Poore page ke liye hum ek hi machine state reuse karenge taaki ek single mental picture par fluency build ho.

Notation reminder (sab parent se): = instruction mein baka hua address/displacement field; = "register ka contents"; = "address par memory ka contents". woh address hai jahan se hum finally operand read karte hain.

Figure — Addressing modes

Upar ki picture dekho: har mode instruction se operand tak ek path hai. Chote paths (immediate, register) kabhi memory touch nahi karte; lambe paths (indirect) use do baar touch karte hain. Neeche ke har exercise ka matlab hai "path trace karo, phir hops count karo."


Level 1 — Recognition

Goal: mode ka naam batao aur directly uska EA rule apply karo.

L1.1

LOAD 500 ek direct instruction hai. kya hai, aur kaunsa operand load hota hai?

Recall Solution

WHAT: Direct mode ka matlab hai address field hi address hai: . WHY: koi register nahi, koi second lookup nahi — bits seedha data ki taraf point karte hain. , operand . Memory accesses = 1.

L1.2

LOAD #500 immediate mode use karta hai. Kaunsa operand load hota hai aur kitne memory accesses hote hain?

Recall Solution

WHAT: # kehta hai operand woh number khud hi hai. Operand . WHY: value instruction word ke andar travel karti hai, isliye koi address kabhi form nahi hota. undefined hai (koi hai hi nahi). Memory accesses = 0.

L1.3

LOAD (R1) register-indirect hai jahan . aur operand do.

Recall Solution

WHAT: register-indirect ka matlab register address hold karta hai: . , operand . Memory accesses = 1. WHY sirf ek: pointer pehle se register mein tha, isliye hum "pointer read karo" wala hop skip kar dete hain.


Level 2 — Application

Goal: ek field aur register combine karo, ya do memory reads chain karo.

L2.1

LOAD (100)memory-indirect mode, . aur operand nikalo.

Recall Solution

Step 1 (WHAT): pointer cell padho. . Toh . Step 2 (WHY): location 100 ek address store karta hai, data nahi; humein use follow karna hoga. Operand . Memory accesses = 2 (pointer read, phir operand read).

L2.2

LOAD 3(R1)displacement/based mode, , . aur operand nikalo.

Recall Solution

WHAT: displacement ek base register mein ek chota constant offset add karta hai: . , operand . Memory accesses = 1. WHY this shape: array ki start point karta hai; constant 3 element index 3 select karta hai. Yahi hai array[3] ka compile hone ka tarika.

L2.3

LOAD 100(R2)indexed mode, (base), (index). nikalo.

Recall Solution

WHAT: same arithmetic, opposite roles — constant base hai aur register vary karta hai: . Operand (hamare table mein nahi hai — point address hai, ). Memory accesses = 1.


Level 3 — Analysis

Goal: accesses ke baare mein reason karo, PC-relative distances, aur side effects.

L3.1

Har instruction ke liye, operand fetch karne ke liye memory accesses ki sankhya batao (instruction fetch count mat karo): LOAD #7, LOAD R1, LOAD 500, LOAD (100), LOAD (R1), LOAD 3(R1).

Recall Solution
  • LOAD #70 (immediate: value instruction mein hai).
  • LOAD R10 (register: operand register mein hai).
  • LOAD 5001 (direct: 500 par ek read).
  • LOAD (100)2 (indirect: pointer read + operand read).
  • LOAD (R1)1 (register-indirect: pointer pehle se register mein).
  • LOAD 3(R1)1 (displacement: ek add, ek read). Pattern: count karo kitni baar tumhe operand tak pahunchne ke liye memory read karni padti hai. Immediate/register = 0; memory ke through ek indirection 1 hop add karta hai.

L3.2

BRANCH +6 jab ho (PC-relative). Kaunsa target address compute hota hai? Ab OS program ko 1000 bytes upar reload karta hai, toh run time par same instruction ke liye hai. Ab target kya hai?

Recall Solution

WHAT: PC-relative ek distance store karta hai: . Original: . Relocated: . WHY it matters: instruction ne "206" store nahi kiya tha. Usne "+6" store kiya tha. Toh loader code jahan bhi drop kare, branch hamesha current point se 6 aage land karta hai — yahi position independence hai. Dekho Instruction Format jahan encoded word mein rehta hai.

L3.3

LOAD (R1)+auto-increment, , . Load hua operand aur instruction ke baad register ki value batao. Phir, R1 ko reload kiye bina, doosra LOAD (R1)+ kya load karega?

Recall Solution

First execution — WHAT/WHY: auto-increment pehle read karta hai phir pointer step karta hai taaki agla access free mein ready ho. , operand . Phir . Second execution: , operand . Phir . Yahi *p++ streaming idiom hai (dekho Pointers and Arrays).


Level 4 — Synthesis

Goal: modes chain karo, ambiguous operands decode karo, aur real hardware structures se connect karo.

L4.1 — Do-level indirection by hand

Kuch ISAs LOAD ((100)) (double indirect) allow karte hain. Ise hamare table par puri tarah trace karo.

Recall Solution

Step 1: innermost pointer: . Step 2: use follow karo: — yeh ab agla pointer hai. Step 3: phir follow karo: operand . , operand . Memory accesses = 3 (har (...) layer ek extra read ka cost add karti hai). Aise hi tum pointer-to-a-pointer chase karte ho; "arrow follow karo" ka har level ek hop add karta hai.

L4.2 — Stack pop with auto-increment

Ek stack neeche grow karta hai (push decrement karta hai, pop increment karta hai). Register R3 = 600 stack pointer hai, . Pop ko LOAD (R3)+ ki tarah model karo. Kaunsi value pop hoti hai, aur baad mein R3 kahan point karta hai?

Recall Solution

WHAT: pop = top padhna, phir pointer ko usse upar le jaana. , popped value . Phir . WHY auto-increment pop ke liye fit hai: read-then-advance order exactly "top item lo, phir stack shrink karo" se match karta hai. (Ek push auto-decrement use karta: pehle neeche move karo, phir likho.) Dekho Stack and Subroutines.

L4.3 — Same , chaar alag operands

use karke, immediate, direct, indirect, aur (100 ko ke saath displacement manke) displacement modes ke under load hua operand compute karo. Ek address field, chaar answers — explain karo kyun.

Recall Solution
  • Immediate #100: operand (literal). 0 accesses.
  • Direct 100: , operand . 1 access.
  • Indirect (100): , operand . 2 accesses.
  • Displacement 100(R2): , operand . 1 access. WHY chaar answers: bits 100 identical hain; Instruction Format mein mode bits decide karte hain ki 100 ka matlab ek value hai, ek address hai, ek pointer ka address hai, ya ek offset hai. Same bits, alag recipe.

Level 5 — Mastery

Goal: design-level reasoning — modes choose karo, total cost count karo, trade-offs argue karo.

L5.1 — Ek loop ka total memory traffic

Ek loop 4 array elements sum karta hai. Version A direct addressing use karta hai 4 alag LOAD instructions ke saath (har ek absolute address name karta hai). Version B ek loop ke andar LOAD (R1)+ use karta hai. Dono ke liye operand memory accesses count karo (instruction fetches aur loop overhead ignore karo).

Recall Solution
  • Version A: 4 direct loads → operand accesses.
  • Version B: 4 auto-increment loads → operand accesses. Operand traffic identical hai (4). B ka asli fayda hai kam instructions aur koi hard-coded addresses nahi: chaar unrolled loads ki jagah ek reusable loop body, aur yeh kisi bhi array ke liye kaam karta hai jis par R1 point kare. Cost instruction count aur code size mein rehti hai, yahan operand reads mein nahi.

L5.2 — Indirect actually kab pay karta hai?

Tumhe ek table se ek element read karna hai jiska location run time par badalta hai (pehle wale code dwara choose kiya gaya). Direct vs indirect compare karo. Kaunsa possible bhi hai, aur access cost kya hai?

Recall Solution

Direct ke liye address compile time par jaanna zaruri hai — impossible agar woh run time par decide hota hai. Toh direct out hai. Indirect run-time address ko ek jaane-maane pointer cell mein store karta hai (maan lo 100): LOAD (100), operand , 2 accesses. Trade-off: indirect 1 extra memory read pay karta hai lekin kisi aise jagah point karne ki ability kharidta hai jo program likhe jaane par pata nahi thi. Woh extra hop run-time flexibility ki kimat hai — exactly wahi Memory Hierarchy tension jo speed aur generality ke beech hai.

L5.3 — RISC vs CISC mode budget

Ek CISC design ek single instruction mein LOAD ((base + index*scale)) offer karta hai. Ek RISC design memory-indirect aur scaling forbid karta hai, sirf register aur displacement modes offer karta hai. Argue karo ki RISC choice zyada instructions lagte hue bhi overall faster kyun ho sakta hai.

Recall Solution

CISC single instruction hide karta hai: ek add (base+index), ek shift (×scale), ek memory read (pointer), aur ek doosra memory read (operand) — ek opcode ke peeche 2 memory accesses + 2 ALU ops tak. Isse decode aur critical path lambi ho jaati hai; sabse slow mode sabke liye clock set karta hai. RISC kaam ko split karta hai kai simple, fixed-length instructions mein (displacement ke saath register mein address compute karo, phir ek LOAD (R)), har ek mein at most 1 memory access. Simpler decode → chota cycle, gehri pipelining, aur compiler pieces ko reorder/overlap kar sakta hai. Verdict: zyada instructions, lekin har ek sasta hai aur cleanly pipeline karta hai — aksar ek net win. Yeh ek trade-off hai, free lunch nahi. Dekho RISC vs CISC.



Recall Feynman recap for a 12-year-old

Har exercise ek treasure hunt thi. Kuch maps khazana seedha unpar likhe hote hain (immediate). Kuch ek jagah dete hain khodne ke liye (direct — ek dig). Kuch ek aisi jagah dete hain jo doosra map hold karti hai (indirect — do digs). Kuch kehte hain "apne dost R1 se shuru karo aur 3 qadam chalo" (displacement). Auto-increment ek aisa dost hai jo har dig ke baad ek qadam aage leta hai, taaki agla dig ready ho. Tumhara poora kaam: map ka rule padho, final X dhundho, aur count karo kitni baar tumhe khodna pada.