Visual walkthrough — CISC vs RISC philosophies

5.1.1 · D2 · Hardware › Instruction Set Architecture (ISA) › CISC vs RISC philosophies

Hum ek hi number dhundh rahe hain: ek program ko kitne seconds lagte hain? Us number ko $T$ (Time ke liye) bolte hain. End tak aap exactly dekhoge ki kaunse knobs $T$ ko upar ya neeche move karte hain.

Step 1 — Ek program asal mein hota kya hai (kaam ginno)

KYA HAI. Ek program, jab run hota hai, toh basically ek lambi list hoti hai chhoti-chhoti commands ki jinhein CPU ek-ek karke manta hai. Har command ek instruction hai. $N$ = CPU ne actually kitne instructions execute kiye, uski total count.

$N$ kyun? Kuch bhi time karne se pehle, hume kaam ginna padega. Aap "yeh trip kaafi lamba tha" tab tak nahi bol sakte jab tak aap nahi jaante kitne steps liye. $N$ hamaari step count hai.

PICTURE. Neeche, ek hi kaam A = A + B do tareekon se likha gaya hai. CISC ek chhote stack of instructions use karta hai (small $N$); RISC ek uncha stack use karta hai (large $N$). Kaam wahi hai, bas tower ki height alag hai.

Step 2 — Instructions instantly khatam nahi hote: cycle

KYA HAI. Ek CPU ki ek heartbeat hoti hai — ek clock jo tick karta hai. Ek tick ek clock cycle hai. Koi bhi instruction "zero time" mein khatam nahi hota; har ek kuch ticks khata hai.

Cycle kyun? Hume effort ki ek aisi unit chahiye jo poore instruction se chhoti ho, kyunki kuch instructions aasaan hote hain (1 tick) aur kuch bhaari (kaafi ticks). Cycle woh ruler hai jisse hum instruction-effort measure karte hain.

PICTURE. Clock ticks ki ek row. Ek simple RISC ADD 1 tick mein fit ho jaata hai. Ek rich CISC ADD [A],[B] (jo secretly load, add, aur store karta hai) kaafi ticks mein failta hai.

Step 3 — Ek tick free nahi hota: iska cost hai seconds mein

KYA HAI. Clock ka har tick ek fixed amount of real time tak rehta hai. Isse $T_c$ bolte hain — cycle time, seconds mein measure kiya jaata hai. 2 GHz clock ek second mein 2 billion baar tick karta hai, toh har tick $T_c=1/(2\times 10^9)=0.5$ nanoseconds ka hota hai.

$T_c$ kyun? CPI ne bataya kitne ticks. Lekin ticks seconds nahi hote jab tak hum nahi jaante ek tick kitna lamba hota hai. $T_c$ exchange rate hai: ticks → seconds.

PICTURE. Ek akela tick apni width nanoseconds mein dikhane ke liye stretch kiya gaya. Simple hardwired RISC control tick ko narrow rehne deta hai (short $T_c$); complex CISC control ek wider tick force karta hai (long $T_c$), kyunki zyada logic settle hona chahiye agla tick aane se pehle.

Step 4 — Teeno knobs ko multiply karke total time nikalo

KYA HAI. Ab units ko chain karo. Hamare paas hai:

$T=\underset{\text{instructions}}{\underbrace{N}}\times \underset{\frac{\text{cycles}}{\text{instruction}}}{\underbrace{\text{CPI}}}\times \underset{\frac{\text{seconds}}{\text{cycle}}}{\underbrace{T_c}}$

Multiply kyun karte hain, aur yahi teen kyun? Dekho units kaise ek chain ki tarah cancel hote hain — yahi poora reason hai ki formula ek product hai, sum nahi:

$\cancel{\text{instr}}\times \frac{\text{cycles}}{\cancel{\text{instr}}}\times \frac{\text{seconds}}{\cancel{\text{cycles}}}=\text{seconds}$

Har factor ek conversion hai: instructions → cycles → seconds. Multiplication (addition nahi) isliye zaroori hai kyunki har stage pichle wale ko scale karta hai — instructions double karo aur cycles-each bhi double karo toh time chaar guna ho jaata hai.

PICTURE. Teen sliders $N$, CPI, $T_c$ label kiye hue, jo ek box mein jaate hain jisko $T$ output milta hai. Koi bhi slider upar karo toh output bar stretch ho jaata hai.

Step 5 — CISC ki chaal: $N$ chhota karo, kahin aur price chukao

KYA HAI. CISC pehle knob par attack karta hai. Ek rich instruction jaise ADD [A],[B] chaar RISC instructions ka kaam karta hai, toh $N$ gir jaata hai.

Yeh ulta kyun pad sakta hai. Us akele instruction ko fir bhi andar load, add, aur store karna padta hai — toh uska CPI high hota hai (kaafi ticks). Aur extra decoding logic tick ko choda kar deta hai, toh $T_c$ bhi badhta hai. CISC ne ek slider neeche kiya aur accidentally doosre do upar dhakail diye.

PICTURE. Phir se wahi teen-slider box, CISC colors mein: $N$ slider girta hai, lekin CPI aur $T_c$ sliders utha jaate hain — output bar $T$ mushkil se chhota hota hai (ya bada bhi ho jaata hai).

Step 6 — RISC ki chaal: $N$ badhne do, CPI aur $T_c$ crush karo

KYA HAI. RISC uncha tower accept karta hai — zyada instructions, bada $N$. Iske badle mein, har instruction simple aur uniform hota hai, toh:

• CPI $1$ ki taraf drive hota hai (har instruction ≈ ek tick, Pipelining ki wajah se),
• $T_c$ chhota ho jaata hai (simple hardwired control, koi microcode nahi jo tick slow kare).

Yeh kyun jeet sakta hai. RISC ne ek slider upar kiya ($N$) lekin doono sliders neeche kheenche (CPI, $T_c$). Agar neeche ke pulls kaafi strong hain, toh product $T$ phir bhi chhota nikalta hai.

PICTURE. RISC colors mein slider box: $N$ badhta hai, lekin CPI aur $T_c$ collapse hote hain, aur output bar $T$ CISC se chhota end hota hai.

Step 7 — Bet par real numbers lagao

KYA HAI. Parent note ke numbers lo aur unhe directly compare karne layak bars mein badlo.

Yahi poora argument kyun hai. RISC ne 50% zyada instructions use kiye ($1.5$M vs $1.0$M) phir bhi 1.65 vs 5.0 mein khatam hua — lagbhag $3\times$ faster. Bada $N$ worth it tha kyunki CPI $4.0\to 1.1$ giri aur $T_c$ $1.25\to 1.0$ giri.

PICTURE. Do stacked-factor bars. CISC ka bar $N$ par chhota hai lekin overall lamba; RISC ka bar $N$ par uncha hai lekin overall kaafi chhota.

Step 8 — Degenerate cases (jab bet buri hoti hai)

KYA HAI. Koi bhi formula hamesha nahi jeetta. Knobs ko extremes tak dhakelte hain.

Case A — CPI 1 tak nahi pahunch sakta. Agar workload dependencies aur cache misses se bhara hai, toh pipelining stall hoti hai aur RISC ka CPI upar creep karta hai. Tab RISC ka bada $N$ bina kisi CPI reward ke hurt karta hai.

Case B — $T_c$ already floored. Agar dono designs same transistor limits hit karte hain, $T_c$ equal ho jaata hai. Battle sirf $N\times \text{CPI}$ tak collapse ho jaati hai, aur clever microcode wala CISC compete kar sakta hai.

Case C — memory bottleneck hai, CPU nahi. Agar program apna life RAM ka wait karte hue bitaata hai, toh $N$, CPI, ya $T_c$ mein se koi bhi zyada matter nahi karta — poori equation memory latency ke aage daab jaati hai. Yahi wajah hai ki modern chips (x86 vs ARM) converge ho gaye: silicon internals caches aur decoders se kam important hain.

PICTURE. RISC vs CISC bars ko har stressed case mein redraw karo — gap chhota hota hai, khatam hota hai, ya ulta bhi ho sakta hai.

Ek-picture summary

Poora walkthrough ek canvas par: teen knobs ($N$, CPI, $T_c$) ek product $T$ mein jaate hain; CISC $N$ drop karta hai lekin baaki dono inflate karta hai; RISC $N$ inflate karta hai lekin baaki dono crush karta hai; winner woh hai jiski product bar chhoti ho — aur break-even condition exactly batati hai kab.

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