Blocking vs non-blocking assignments: Worked examples

Intuition What this page is

The parent note gave you the rule. Here we stress-test it against every situation a real design (or an exam) can throw at you. We will simulate each always block by hand, step by step, using the two-region scheduler idea: first the Active region (blocking updates happen now, non-blocking right-hand sides get sampled and stashed), then the NBA region (all stashed non-blocking values are written to their targets at once).

Before we start, one vocabulary anchor so no symbol is unearned:

RHS = "right-hand side" = the expression to the right of = or <= (the value being read).
LHS = "left-hand side" = the register being written.
"Old value" = the value a register held just before this clock tick. "New value" = what it holds just after.
A register (reg) is a named storage cell — see Verilog data types (reg vs wire). On a clock edge it can hold a fresh value.

The scenario matrix

Every worked example below fills one cell of this table. Together they cover all of them.

#	Cell (case class)	Example that covers it
C1	Sequential swap — `<=` vs `=` side by side	Example 1
C2	Shift register / pipeline — order-independence of `<=`	Example 2
C3	Combinational chain — `=` is required	Example 3
C4	Degenerate input: self-assign / initial `x` (unknown) values	Example 4
C5	Mixed operators on same var — the illegal/ambiguous case	Example 5
C6	Two always blocks driving related signals — race condition	Example 6
C7	Limiting case: a counter over many cycles (`=` vs `<=` divergence over time)	Example 7
C8	Real-world word problem: traffic-light-style state + output register	Example 8
C9	Exam twist: reordered lines + a read of a just-written signal	Example 9

We trace numeric values everywhere so simulation outcomes are concrete, not hand-wavy.

Example 1 — The swap (cell C1)

Forecast: guess the two (a, b) pairs before reading on.

Version NB (non-blocking):

Active region — sample all RHS from old values. Why this step? <= reads pre-edge values. Old a = 3, old b = 7. So we stash: a's pending value $= 7$ , b's pending value $= 3$ .
NBA region — write both at once. Why this step? All stashed writes land together. Result: a = 7, b = 3. Swapped.✔

Figure — Blocking vs non-blocking assignments

Version B (blocking):

a = b → a becomes 7 immediately. Why this step? = updates now, before line 2.
b = a → but a is already 7, so b = 7. Why this step? Line 2 sees the freshly-written a.
Final: a = 7, b = 7. No swap.✘

Recall Verify (sanity check)

Non-blocking preserves the pair as a set: {3,7} before, {7,3} after — a genuine permutation. Blocking loses the value 3 entirely (information destroyed) — a tell-tale sign the swap failed.

Example 2 — Shift register, and why order can't matter (cell C2)

Forecast: does reordering change (q1, q2, q3)?

Sample every RHS from old values (Active region). Why? Every <= reads pre-edge. Stash: q3 ← q2_old = 1, q2 ← q1_old = 0, q1 ← d = 1.
Write together (NBA region). Result: q1 = 1, q2 = 0, q3 = 1.
Reorder proof. Why unchanged? Step 1 read all three RHS before any LHS was written. Shuffling the lines shuffles nothing that step 1 depends on — the old values are fixed. Same hardware, same result.✔

Contrast with blocking (q1=d; q2=q1; q3=q2;): q1 becomes 1, then q2 = q1 = 1, then q3 = q2 = 1. In one clock d reached q3. Why wrong? Immediate updates let the value ripple through — you built one flip-flop, not a three-stage pipeline.

Recall Verify

After three clocks of the correct <= version, a 1 injected at d walks q1 → q2 → q3. That "one stage per clock" delay is exactly the definition of a shift register; the blocking version delivers it in zero extra clocks (collapsed).

Example 3 — Combinational chain where `=` is mandatory (cell C3)

Forecast: what is y? What would <= give instead?

tmp = a & b → 1 & 1 = 1, applied now. Why blocking? This is pure data-flow (combinational logic); tmp must be ready before y reads it, like a signal rippling through gates.
y = tmp | c → 1 | 0 = 1. Why? Line 2 must see the fresh tmp. Correct answer y = 1.✔
If we used <=: tmp <= a&b samples but does not update in this pass, so line 2 reads the old tmp → stale y, and the tool may infer an unwanted latch → a sim/synthesis mismatch.

Recall Verify

Boolean truth: with a=b=1, c=0, $(a \land b) \lor c = 1$ . Blocking gives 1; non-blocking (reading stale tmp = 0 on the very first evaluation) would give 0 — provably wrong.

Example 4 — Degenerate inputs: self-assign & unknown `x` (cell C4)

Worked example Statement

A register r is uninitialized (Verilog value x = "unknown"). Two edges of:

always @(posedge clk) r <= r;   // self non-blocking assign

Separately, what does r = r; (blocking self-assign) do?

Forecast: does r ever become known? Any difference between = and <= here?

r <= r, first edge. Sample RHS = old r = x. Write back x. Why no change? A register assigned only its own old value is a hold; unknown stays unknown. It never resolves to 0 or 1 on its own.
Second edge: identical — still x. This is the degenerate "does nothing but hold" flop.
Blocking r = r: reads r, writes the same r immediately — also a no-op, same x. Why identical here? With a single self-referential statement there is no later line to observe the difference, so = and <= coincide.
Lesson on degeneracy: the blocking/non-blocking distinction only becomes visible when one statement's result is read by another statement in the same block. Self-assign has no such reader.

Recall Verify

x under any bitwise identity op is x. So both versions leave r = x for all cycles — a fixed point. The two operators are indistinguishable in this degenerate single-statement case.

Example 5 — Mixing `=` and `<=` on the same variable (cell C5)

Worked example Statement

n = 2 initially. On one edge:

always @(posedge clk) begin
    n  = n + 1;   // blocking
    n <= n + 10;  // non-blocking, SAME variable
end

What is n after the edge? Why is this forbidden by Rule 3?

Forecast: guess the final n.

n = n + 1 (blocking) → n becomes 3 immediately. Why? = updates now.
n <= n + 10 (non-blocking) samples RHS using the current n = 3 → stashes 13, applied in the NBA region.
NBA region: n = 13. So the blocking write of 3 is overwritten. Final n = 13.
Why forbidden? The outcome depends on a subtle read/write ordering across two scheduler regions. A different tool or a reordered line changes the answer → classic ambiguity. Golden Rule 3: never mix operators on one variable.

Recall Verify

Trace: start 2 → blocking makes 3 → NBA RHS sampled as $3 + 10 = 13$ → NBA writes 13. Final = 13. The intermediate 3 is transient and unobservable, which is exactly why this style is dangerous.

Example 6 — Two always blocks, one race (cell C6)

Forecast: does splitting the swap across two blocks break it?

Both blocks trigger on the same edge. Each <= samples its RHS from old values in the Active region: Block 1 stashes a ← 9, Block 2 stashes b ← 5. Why safe here? Non-blocking sampling reads pre-edge values regardless of which block ran first.
NBA region writes both: a = 9, b = 5. Correct swap — no race.✔
The race version: if instead both used blocking (a = b; in one block, b = a; in another), the result depends on which block the simulator runs first — an undefined ordering across separate blocks. That is a true race condition.
Caveat (Golden Rule 4): even the correct <= version drives two different variables from two blocks — fine. Driving the same variable from two blocks is what's illegal.

Recall Verify

<= across two blocks: {5,9} → {9,5}, a clean permutation. Blocking across two blocks yields either {9,9} or {5,5} depending on run order — provably non-deterministic.

Example 7 — Limiting case: divergence over many cycles (cell C7)

Worked example Statement

Two counters, both start at 0. Every clock:

// Counter A (non-blocking)   // Counter B (blocking, buggy feedback)
cnt <= cnt + 1;               nxt = cnt + 1; cnt = nxt; cnt = cnt + 1;

After 4 clocks, what is each cnt? This shows the long-run limiting behaviour.

Forecast: guess both values after 4 clocks.

Counter A: each edge samples old cnt, adds 1, writes once. Sequence: 0 → 1 → 2 → 3 → 4. After 4 clocks, cnt = 4. Why? Exactly one increment per edge — the intended counter.
Counter B: per edge, nxt = cnt+1 then cnt = nxt then cnt = cnt+1 → two increments applied immediately each edge. Sequence: 0 → 2 → 4 → 6 → 8. After 4 clocks, cnt = 8.
Limiting insight. Why care about "many cycles"? A one-cycle test might look "close enough," but the error compounds linearly: Counter B runs at double rate, drifting further every clock. The bug is invisible at cycle 0 and glaring at the limit.

Recall Verify

A after $n$ clocks $= n$ ; B after $n$ clocks $= 2 n$ . At $n = 4$ : A $= 4$ , B $= 8$ . The gap $= n$ grows without bound.

Example 8 — Real-world word problem: state + output register (cell C8)

Worked example Statement

A pedestrian crossing controller has a state register state (0 = WALK, 1 = STOP) and an output register light that should show the STOP lamp one clock after entering STOP (a registered output, no glitches). Model one edge where we transition WALK→STOP. Which operator, and what are state, light after the edge if before it state = 0 (WALK), light = 0?

always @(posedge clk) begin
    state <= 1;          // go to STOP
    light <= state;      // register the OLD state onto the lamp
end

Forecast: after this edge, is light already 1, or still 0?

Sample RHS from old values. Why <=? This is clocked sequential logic; a registered output must reflect the pre-edge situation to stay glitch-free. Stash state ← 1, light ← old state = 0.
NBA writes: state = 1, light = 0. So the lamp lags the state by exactly one clock — precisely the intended "one clock later" behaviour.
Next edge (now old state = 1): light <= state stashes 1 → light = 1. The STOP lamp lights one clock after the state changed. ✔
Why not blocking? light = state after state = 1 would show 1 the same cycle, defeating the registered-output timing and risking a decode glitch.

Recall Verify

Edge 1: (state,light): (0,0) → (1,0). Edge 2: (1,0) → (1,1). The output is a one-cycle delayed copy of the state — the hallmark of a registered output.

Example 9 — Exam twist: read a just-written signal (cell C9)

Worked example Statement

p = 4, q = 0. A single clocked block:

always @(posedge clk) begin
    p <= p + 1;
    q <= p;        // reads p — but which p?
end

Then the twist: swap the two lines and re-trace. Does q change?

Forecast: after the edge, what are p and q? And after swapping lines?

Sample all RHS from old values (Active region). Why? <= never sees a same-cycle update. Old p = 4. Stash p ← 5, q ← old p = 4.
NBA writes: p = 5, q = 4. So q gets the old p, not the incremented one.
Swap the lines (q <= p; first, then p <= p + 1;): still samples old p = 4 for both. Result identical: p = 5, q = 4. Why? Order-independence of <= (Example 2's principle).
Common exam trap: students expect q = 5 because line 2 is "after" line 1. But <= breaks the software intuition — line 2 reads the pre-edge p.

Recall Verify

p_new = p_old + 1 = 5; q_new = p_old = 4, independent of line order. If a student answers q = 5 they've fallen for the blocking-style intuition.

Wrap-up: the matrix, filled

Active Recall

Value of n after Example 5's edge?

13 — the non-blocking NBA write (

3 + 10

) overwrites the transient blocking 3.

Counter B's value after 4 clocks (Example 7)?

8 — two increments per edge, so

2 \times 4

(p, q) after Example 9's edge?

p = 5, q = 4; q reads the pre-edge p, unaffected by line order.

After a WALK→STOP transition, when does the lamp light (Example 8)?

One clock after the state changes, because the registered output samples the old state.

Connections

Blocking vs non-blocking assignments (parent)
Always blocks and sensitivity lists
Combinational vs Sequential logic
D Flip-Flops and Registers
Race conditions in RTL simulation
Synthesis vs Simulation mismatch
Verilog data types (reg vs wire)
Pipelining and shift registers