Exercises — Blocking vs non-blocking assignments

• always @(posedge clk) → <= (non-blocking). Clocked flip-flops all update together on the edge using the pre-edge picture.
• always @(*) → = (blocking). Combinational logic is a data-flow: each intermediate must be ready before the next line uses it.

Mnemonic from the parent: "Clock? Non-blocK."

• x = a; → B
• y <= b; → N
• z <= c; → N

The single = is blocking; <= (which looks like a "delay arrow") is non-blocking.

Non-blocking: sample all RHS first using pre-edge values → RHS of line 1 is old b = 7, RHS of line 2 is old a = 3. Then apply both.

• a = 7, b = 3. The values swap. ✔

Blocking updates immediately, in order:

• Line 1: a = b → a becomes 7.
• Line 2: b = a → but a is already 7, so b = 7.
• Result: a = 7, b = 7. No swap — both hold old b. ✘

Blocking, in order:

• c = a + b = 2 + 5 = 7 (uses the current a = 2).
• a = 10 happens after — it does not retro-change c.
• So c = 7, and a = 10. (In real combinational hardware, changing a afterward re-triggers @(*) and re-runs, but within this single pass c = 7.)

Blocking makes each line apply immediately, so d ripples through all three in one edge:

• q1 = d
• q2 = q1 → now = d
• q3 = q2 → now = d After one clock, q1 = q2 = q3 = d. All three collapse to the same value — the synthesizer builds effectively one flip-flop plus wires, not three stages. See the Pipelining and shift registers note for the intended structure. Fix: use <=, which samples pre-edge values so each stage receives its neighbour's old value.

With <=, tmp is not updated until the end of the pass, so line 2 uses the stale (previous) tmp, not the freshly-computed a & b. The simulator models a wrong/latched value, and it disagrees with the synthesized gate netlist → a classic Synthesis vs Simulation mismatch. The tool may even infer an unintended latch on tmp. Fix: combinational data-flow needs =, so tmp is ready before y reads it.

q is assigned from two different clocked blocks. Both fire on the same edge; the two non-blocking updates to the same LHS collide with no defined ordering → a race condition. The final value of q is simulator-dependent, and synthesis will complain about multiple drivers. Fix (Golden Rule 4): each variable is driven by exactly one always block. Merge the logic (e.g. q <= sel ? e : d;).

Clocked ⇒ non-blocking:

always @(posedge clk) begin
    q1 <= d;
    q2 <= q1;
    q3 <= q2;
    q4 <= q3;
end

Each stage grabs its neighbour's old value, so data advances exactly one stage per clock. See D Flip-Flops and Registers.

Combinational ⇒ blocking =, and list all inputs (or use @(*)):

always @(*) begin
    p = a & b;   // ready first
    y = p | c;   // uses fresh p
end

= makes p available immediately for the next line, matching how a signal ripples through gates. Using <= would feed line 2 a stale p.

Clocked ⇒ non-blocking; synchronous reset is inside the clocked block:

always @(posedge clk) begin
    if (rst)
        count <= 0;
    else
        count <= count + 1;
end

count <= count + 1 samples the old count, adds 1, and defers the update — exactly one increment per edge, no runaway.

Step through the scheduler:

• Active region: a = a + 1 (blocking) applies immediately → a becomes 2.
• Then the <= RHS is sampled using the current a = 2 → stashed value = 2 + 2 = 4.
• NBA region: apply the stash → a = 4. Final a = 4. But this violates Golden Rule 3 — mixing = and <= for the same variable creates fragile, hard-to-read, tool-dependent behaviour. Never write this in real RTL; the answer is a trap, not a technique.

Both blocks sample RHS from pre-edge values, then update in the NBA region. Different variables ⇒ no illegal double-drive.

• After edge 1: sample old x = 1, y = 0 → new x = y = 0, new y = x = 1. So x = 0, y = 1 (they swapped).
• After edge 2: sample x = 0, y = 1 → x = 1, y = 0 (swap back). They ping-pong every clock: (1,0) → (0,1) → (1,0) → …. This is the multi-block version of the swap example, and it works precisely because <= uses the old picture.

• tmp = sel ? a : b blocking → sel = 1, so tmp = a = 4, applied immediately.
• out <= tmp + 1: RHS sampled now using tmp = 4 → stash = 5; applied in NBA region.
• Final out = 5. The blocking tmp is fine here because it is fully computed and consumed within the same pass before the deferred <= samples it. out is still a clean edge-triggered flip-flop.

L1: clock→<=, combinational→=. <= is assignment, not comparison. L2: <= swap works (old values); = swap fails (both = old b). L3: blocking shift register collapses to one flop; <= in combinational uses stale intermediates; two blocks on one var = race. L4: shift register / combinational chain / counter — correct operators as shown. L5: mixed operators are traceable but forbidden; cross-coupled <= ping-pongs; blocking scratch + <= output is legal.