Intuition The one core ideaDigital hardware is a room full of tiny memory boxes that all change their held value at the exact same instant — the tick of a shared clock — and between ticks they simply remember. Everything on the parent page (always, <=, posedge, flip-flops, latches) is just notation for describing when a box updates and what it grabs at that moment.
This page assumes you have seen nothing . We build every word, symbol, and picture the parent Sequential logic note leans on, in an order where each idea needs only the ones before it.
Definition Bit and signalA bit is a single wire that carries a value. Most of the time that value is one of two voltages, which we name 0 (low) and 1 (high). A signal is a named wire (or bundle of wires) whose value we track over time.
Intuition Real wires have four states, not twoVerilog models a wire with four possible values, because real hardware needs more than just 0 and 1:
0 — low.1 — high.X — unknown : the simulator does not know whether it is 0 or 1 (e.g. a flip-flop before reset). X is a warning flag, not a real voltage.Z — high-impedance : the wire is driven by nobody — floating, disconnected.
For this foundations page we mostly reason with 0 and 1, but remember X and Z exist — an X on Q in simulation usually means "you forgot to initialise or reset something."
The picture to hold in your head: a wire is a horizontal line, and as time flows left→right the line sits either low or high . That squared-off up-and-down trace is called a waveform .
Intuition Why we need this firstEvery later symbol (clk, d, q) is just a named signal. If you can read a waveform, you can read the whole topic.
A clock (clk) is a special signal that flips 0→1→0→1 forever at a steady rhythm. It is the shared drumbeat everyone in the circuit listens to.
The picture: on the clock waveform, an edge is the vertical line connecting a low level to a high level (or vice-versa). It has essentially zero width — it is a moment , not a duration.
Intuition Why "edge" and not "level"?If hardware reacted to the level (the flat high part), it would keep re-triggering the whole time the clock is high. Reacting to the edge means it fires exactly once per cycle — one clean update per drumbeat. This "fire on the rising instant" idea is exactly what the parent's clocked blocks use; we give it its formal notation in Section 4 .
Definition Holding a valueTo "remember," a circuit needs an element that keeps its output the same until told to change. Two flavours exist:
A latch updates whenever the clock is at a level (e.g. all the time clock is high) — it is "transparent" during that whole window.
A flip-flop updates only at an edge — one snapshot per cycle.
Intuition Why we prefer flip-flopsA latch that is transparent for a whole half-cycle lets new input ripple through unpredictably; timing becomes hard. A flip-flop takes one crisp photo at the edge and holds it, so every box in the design freezes its value at the same trustworthy instant. This is why the parent's accidental "inferred latch" is a bug — you wanted a clean snapshot, you got a transparent window instead. More detail in D flip-flops and latches .
The signal names that go with a flip-flop:
==D (data) is the input wire — the value waiting to be captured. Q== is the output wire — the value currently being held and shown to the world. At the active edge, the flop copies D into Q. (Before the first edge, Q often reads as X — unknown — until a reset sets it.)
Definition Combinational logicCombinational logic has no memory : output is purely a function of the present inputs. Change an input, the output re-computes right away. Built with assign statements or always @(*).
Definition Sequential logicSequential logic has memory : output depends on inputs and on stored past values (held in flip-flops), updated only at clock edges.
Recall The two-kids picture (from the parent)Combinational kid shouts the answer the instant they see the question. Sequential kid only flips their whiteboard around when the teacher rings the bell (clock), holding the old answer until then.
always block
An ==always block== is a chunk of Verilog that re-runs its body whenever a signal in its sensitivity list changes. It is not a loop — it is event-driven: it fires, does the body once , then sleeps until the next trigger.
@(...) symbol
@ means "sensitive to." The parentheses hold the trigger. This is the first time we formally use the @(...) notation, so read the two cases carefully:
@(posedge clk) → fire on the rising edge (the 0→1 instant from Section 1) only → sequential .@(*) → fire on any change of any signal read inside → combinational .
always means a fast infinite loop"
Why it feels right: the English word "always". Reality: it sleeps between events. Read always @(posedge clk) as "each time the clock rises, do this body once."
These are the symbols people trip on most, so we define them on a picture, not in prose.
=
==Blocking === runs immediately, in order , like normal software: line 1 finishes and updates its variable before line 2 reads anything. Order = data flow.
<=
==Non-blocking <=== does two phases: (1) read all right-hand sides using the old values, then (2) update all left-hand sides together. This is exactly a rank of flip-flops snapping at the same edge.
Why the difference matters concretely is the whole subject of Blocking vs non-blocking assignments . The short version: real flops all sample the old input at once, so <= (evaluate-old-then-update-together) is the faithful model; = (one at a time) collapses a shift register. Getting this wrong causes Synthesis vs simulation mismatch .
1'b0 and friends
1'b0 reads as "1 bit, in b inary, value 0 ." So 1'b1 is a one-bit high. The if / else inside a block chooses which assignment happens, giving priority to whichever branch is checked first (used for reset priority on the parent page).
posedge rst in the list
Putting rst (reset) in @(posedge clk or posedge rst) makes reset asynchronous — it acts the instant reset rises, without waiting for a clock edge. Leaving it out makes reset synchronous — it only clears on the next clock edge.
combinational vs sequential
always block and sensitivity list
blocking = vs non-blocking arrow
Sequential logic and always blocks
This foundation feeds forward into Finite State Machines in Verilog , Clocking and timing constraints , and the parent note itself.
Cover the right side, answer, then reveal.
A bit is a single wire carrying a value; usually 0 (low) or 1 (high).
The four Verilog wire values are 0, 1, X (unknown) and Z (high-impedance / floating).
What does an X on Q usually mean? an uninitialised / un-reset value the simulator cannot resolve.
A waveform shows a signal's value (high/low) as time flows left to right.
An edge is the instant a signal changes value; posedge = the 0→1 moment.
Why fire on an edge, not a level? so the box updates exactly once per clock cycle, not continuously while the clock is high.
A flip-flop vs a latch flip-flop snapshots D into Q only at the edge; a latch is transparent for a whole clock level.
D and Q are D is the input waiting to be captured, Q is the held output value.
Combinational logic has no memory; output depends only on present inputs.
Sequential logic has memory; output depends on inputs plus stored past values.
An always block is an event-driven process that runs its body once each time a sensitivity-list signal changes (not a loop).
@(posedge clk) meansfire on the rising edge of clk → sequential logic.
@(*) meansfire on any change of any signal read inside → combinational logic.
Blocking = does immediate, in-order updates like normal software.
Non-blocking <= does evaluate all RHS with old values, then update all LHS together — models parallel flops.
The golden pairing sequential → <=, combinational → =.
1'b0 meansa one-bit binary value of 0.
Async vs sync reset async reset is in the sensitivity list and acts immediately; sync reset only clears on the next clock edge.
