Exercises — Sequential logic and always blocks

• (a) Combinational. Trigger: any change of a read signal (a or b), because @(*) auto-builds the sensitivity list. No clock → no memory.
• (b) Sequential. Trigger: the rising clock edge (posedge clk). One flip-flop.
• (c) Sequential with an active-low asynchronous reset. Trigger: posedge clk for normal capture, negedge rstn for reset. rstn is in the list, so reset acts immediately, not on the clock. This is the reset style built step-by-step in D flip-flops and latches — reset that does not wait for the clock.

• (a) combinational → blocking =. Order equals data-flow, so evaluating in program order is correct.
• (b) sequential → non-blocking <=. All right-hand sides must be read from old values so parallel flip-flops update together.

reg q;                        // 1-bit storage box for the flip-flop
always @(posedge clk) begin   // rst NOT in the list → synchronous
  if (rst) q <= 1'b0;         // reset checked first = priority
  else     q <= d;
end

Why rst is not in the sensitivity list: synchronous reset only takes effect at a clock edge. Why if (rst) first: reset must dominate normal capture.

reg [3:0] count;                // 4-bit box, holds 0..15
always @(posedge clk or posedge rst) begin
  if (rst) count <= 4'b0000;    // async → rst in the list
  else     count <= count + 1;  // non-blocking: reads OLD count
end

Why <=: the right side reads the old count, adds 1, then commits — modelling one register that clocks once per edge. Start at 0000; after 15 edges it reads 1111 and the next edge wraps to 0000 (a 4-bit value rolls over modulo $2^4=16$).

Just before edge 1, count = 0 (reset value). Each edge adds 1, so the six requested values — the state after edges 1…6 — are: $\underset{\text{after 1}}{\underbrace{1}}\to 2\to 3\to 4\to 5\to \underset{\text{after 6}}{\underbrace{6}}$ In 4-bit binary: 0001, 0010, 0011, 0100, 0101, 0110. The pre-edge 0000 is the starting state, not one of the six reported outputs. The waveform below traces exactly these steps — read the red count line changing one tick after each rising edge.

Version N — non-blocking. All RHS read the old values a=1, b=2, c=3 first, then commit: $a\leftarrow b_{old}=2,b\leftarrow c_{old}=3,c\leftarrow a_{old}=1$ Result: a=2, b=3, c=1 — a clean 3-way rotation.

Version B — blocking. Executes top-to-bottom, each line sees the just-updated value:

• a = b → a = 2
• b = c → b = 3
• c = a → c = 2 (uses the new a, not old!)

Result: a=2, b=3, c=2 — the rotation is broken; 1 is lost.

The figure below puts both versions side by side: the black arrows in Version N all reach back to the old values, while the red arrow in Version B feeds the just-written a forward — that single red arrow is why the 1 disappears.

When sel == 2'b11, no branch assigns y. Verilog interprets "keep the last value" as memory, so the synthesizer infers a latch on y — an unwanted 1-bit storage element in what should be pure combinational logic. In Combinational logic and assign statements the same job is done safely with a single assign and a full ternary, which is impossible to leave incompletely specified. Fix (either works):

always @(*) begin
  y = a;                    // default at top, then override
  if (sel == 2'b01) y = b;
  else if (sel == 2'b10) y = c;
  else if (sel == 2'b11) y = 1'b0;
end

Now y is assigned on every path → no latch.

reg q1, q2, q3;               // three 1-bit boxes, one per stage
always @(posedge clk) begin
  q1 <= din;   // reads OLD din
  q2 <= q1;    // reads OLD q1
  q3 <= q2;    // reads OLD q2
end

Why <= is mandatory: each line must read the pre-edge value of the previous stage. With <=, all three RHS are sampled from old values, then committed together — so a bit truly moves one stage per edge. If you used blocking =, line 2 would see the new q1 and the whole register would collapse into a single stage.

Each edge: q1←din, q2←old q1, q3←old q2. Start (0,0,0).

Notice the first 1 (from edge 1) reaches q3 exactly on edge 3 — three stages, three cycles of delay. The waveform below shows this: follow the red highlight tracking that first 1 marching one stage to the right per clock.

reg state;                    // 1-bit box holding the FSM state
always @(posedge clk or posedge rst) begin
  if (rst)      state <= 1'b0;
  else if (en)  state <= ~state;  // flip
  else          state <= state;   // hold (explicit is clearest)
end

Why the explicit else state <= state: it documents the hold. In a clocked block the omission is safe (a flop naturally holds), unlike the combinational latch case in 3.2. This one-flip-flop toggle is the smallest example of the state-register pattern generalised in Finite State Machines in Verilog, where the same clocked block updates a multi-bit state.

A 3-bit register counts modulo $2^3=8$.

• After 1 edge: $6+1=7$ → 111.
• After 3 edges: $(6+3)\mathrm{mod}8=9\mathrm{mod}8=1$ → 001.

Why the wrap: 7 + 1 = 8 needs 4 bits, but only 3 exist, so the top bit is discarded, leaving 000. Counting continues 0,1,... — this is exactly arithmetic modulo 8.

• Student A: the sensitivity list is missing c. Simulation: the block only re-runs when a or b changes; a change in c alone leaves y stale (wrong). Synthesis: the synthesizer reads the body, sees c, and builds the full AND gate anyway. → the block behaves one way in the simulator and another in silicon, the classic hazard catalogued in Synthesis vs simulation mismatch.
• Student B: @(*) auto-includes a, b, c. Simulation and synthesis agree. ✅
• Correct: Student B. Always use @(*) for combinational logic so no signal is ever forgotten.

The right side q + 1 is evaluated using the old value of q (the value before the edge). That result is then committed to the left q once, at the end of the edge. The block does not re-run just because q changed — as the parent note on always blocks stresses, an edge-triggered block is event-driven and wakes only on the next posedge clk. So each edge adds exactly one; no runaway loop. Contrast a combinational always @(*) q = q + 1;, where q changing would re-trigger the block → an illegal combinational loop. The clock edge is precisely what tames the feedback.

Clocked → <=. Combinational → = with @(*). Async reset → in the sensitivity list, checked first. Every combinational branch assigns every output (else latch). One register → one always. N-bit register wraps modulo $2^N$. always is event-driven, not a loop.