ALU design fundamentals: Worked examples — Hardware deep dive

Intuition What this page does (and why)

The parent note showed you how an ALU is built. But a circuit only earns your trust when it survives every kind of input you can throw at it. So here we hunt down each scenario class — positive results, negative results, zero, the two overflow types, a logic operation, and a real "gotcha" exam trap — and we work one full example for each cell. When you finish, no 4-bit ALU situation will ever surprise you.

Everything below uses 4-bit numbers, so results live in $F_{3} F_{2} F_{1} F_{0}$ and there is a final carry $c_{4}$ . Two symbols we lean on constantly, defined in plain words first:

$c_{k}$ = the ==carry that crosses from bit position $k - 1$ into bit position $k$ ==. Think of it as the little "1 I carried over" in grade-school addition, but there is one at every column boundary.
$c_{4}$ = the carry that falls off the left end (out of the top bit). It has nowhere to go inside a 4-bit box, so we catch it in the ==Carry flag $C$ ==.

The scenario matrix

Before working anything, let us list every case class a 4-bit ALU can produce. If we cover all rows, we have covered the topic.

#	Cell (scenario class)	What is special about it	Example that hits it
1	Add, result fits (positive)	ordinary case, no flags fire	Ex 1
2	Add, signed overflow	$c_{4} \neq = c_{3}$ , sign corrupted	Ex 2
3	Add, unsigned carry-out	$c_{4} = 1$ but signed still valid	Ex 3
4	Subtract, positive result	$A > B$ , $C = 1$ = no borrow	Ex 4
5	Subtract, negative result	$A < B$ , $C = 0$ = borrow, $N = 1$	Ex 5
6	Zero / degenerate result	$F = 0000$ , Zero flag $Z = 1$	Ex 6
7	Logic op (AND/OR/XOR)	no carries; $C, V$ meaningless	Ex 7
8	Real-world word problem	temperature "wrap-around"	Ex 8
9	Exam twist	same bits, two interpretations	Ex 9

Each example is tagged with the cell it fills.

Figure s01 below shows which bit each flag reads from — keep it in view; Example 2 refers back to the flag positions drawn here.

The worked examples

Worked example Example 1 — Cell #1: Add, positive result that fits

Compute $A = 0010 (2) + B = 0011 (3)$ with $S_{s u b} = 0$ (pure add, so carry-in $c_{0} = 0$ ).

Forecast: guess the 4 result bits and all four flags before reading on. Does anything overflow?

Line up the columns and add right-to-left, tracking each carry. Why this step? A full adder only ever adds three bits per column ( $a_{i}, b_{i}, c_{i}$ ); the carry is the whole story of how columns talk to each other.
- bit0: $0 + 1 + 0 = 1$ → $F_{0} = 1$ , $c_{1} = 0$
- bit1: $1 + 1 + 0 = 10$ → $F_{1} = 0$ , $c_{2} = 1$
- bit2: $0 + 0 + 1 = 1$ → $F_{2} = 1$ , $c_{3} = 0$
- bit3: $0 + 0 + 0 = 0$ → $F_{3} = 0$ , $c_{4} = 0$
Result $F = 0101 (5)$ .
Read off the flags. Why this step? The whole point of an ALU is to report what happened; each flag is a cheap function of bits we already computed, so we harvest them now.
- $Z = 0$ (not all zero), $C = c_{4} = 0$ , $N = F_{3} = 0$ , $V = c_{4} \oplus c_{3} = 0 \oplus 0 = 0$ .

Verify: $2 + 3 = 5$ ✓. As signed numbers $+ 2$ and $+ 3$ are both in range, sum $+ 5 \leq 7$ in range, so $V = 0$ is right. As unsigned, $5 \leq 15$ , so $C = 0$ is right. Every flag consistent.

Worked example Example 2 — Cell #2: Add with

signed overflow (two positives make a "negative") Compute $A = 0101 (5) + B = 0011 (3)$ , $S_{s u b} = 0$ . (This is the parent note's Example 1 — we dissect its carries.)

Forecast: $5 + 3 = 8$ . But 4-bit signed range is $- 8 \dots 7$ . Where does $8$ land?

Add column by column. Why this step? We must see the carry cross into the sign bit — that crossing is the whole overflow story.
- bit0: $1 + 1 + 0 = 10$ → $F_{0} = 0$ , $c_{1} = 1$
- bit1: $0 + 1 + 1 = 10$ → $F_{1} = 0$ , $c_{2} = 1$
- bit2: $1 + 0 + 1 = 10$ → $F_{2} = 0$ , $c_{3} = 1$
- bit3: $0 + 0 + 1 = 1$ → $F_{3} = 1$ , $c_{4} = 0$
Result $F = 1000$ .
Compare the two carries at the sign bit. Why this step? $V = c_{4} \oplus c_{3}$ ; a mismatch here is the definition of signed overflow. Look at Figure s02: the carry $c_{3} = 1$ entered the sign column but $c_{4} = 0$ left it — a disagreement.
- $V = c_{4} \oplus c_{3} = 0 \oplus 1 = 1$ → signed overflow!
Read the remaining three flags. Why this step? Overflow alone does not tell the CPU the number or its sign; we still need $Z, C, N$ to fully describe the result, so we finish the report.
- $Z = 0$ , $C = c_{4} = 0$ , $N = F_{3} = 1$ .

Verify: unsigned, $5 + 3 = 8 = 100 0_{2}$ ✓ (and $8 \leq 15$ so $C = 0$ correct). Signed, $1000$ is $- 8$ , not $+ 8$ — the answer wrapped past $+ 7$ , exactly what $V = 1$ warns you about. ✓

Worked example Example 3 — Cell #3: Add with

unsigned carry-out but no signed overflow Compute $A = 1111 (15 unsigned, - 1 signed) + B = 0010 (2)$ , $S_{s u b} = 0$ .

Forecast: which flag fires — $C$ , $V$ , both, or neither? These are two different overflows and this example separates them cleanly: we want $C = 1$ (unsigned overflowed) but $V = 0$ (signed still fine).

Add, tracking $c_{3}$ and $c_{4}$ separately. Why this step? We need both sign-column carries explicitly, because $V = c_{4} \oplus c_{3}$ depends only on whether they match — so we must record each.
- bit0: $1 + 0 + 0 = 1$ → $F_{0} = 1$ , $c_{1} = 0$
- bit1: $1 + 1 + 0 = 10$ → $F_{1} = 0$ , $c_{2} = 1$
- bit2: $1 + 0 + 1 = 10$ → $F_{2} = 0$ , $c_{3} = 1$
- bit3: $1 + 0 + 1 = 10$ → $F_{3} = 0$ , $c_{4} = 1$
Result $F = 0001 (1)$ , with $c_{3} = 1$ and $c_{4} = 1$ .
Read the flags. Why this step? This example exists to contrast $C$ and $V$ ; only by computing both do we see that a carry-out can happen while the signed answer stays perfectly valid.
- $Z = 0$ , $C = c_{4} = 1$ , $N = F_{3} = 0$ , $V = c_{4} \oplus c_{3} = 1 \oplus 1 = 0$ . $C = 1$ but $V = 0$ — the cell we wanted.

Verify (unsigned view): $15 + 2 = 17$ ; 4 bits hold $0 \dots 15$ , so $17$ needs a 5th bit — that is $c_{4} = 1$ , and the kept bits $0001$ are $17 - 16 = 1$ . So $C = 1$ correctly flags unsigned overflow. ✓ Verify (signed view): $1111 = - 1$ and $0010 = + 2$ , so $(- 1) + 2 = + 1$ , which fits in $[- 8, 7]$ — no signed overflow, so $V = 0$ is right. Contrast this with Ex 2 (overflow but no carry) and Ex 9 (carry but no overflow, result zero). ✓

Worked example Example 4 — Cell #4: Subtract, positive result (

$A > B$ ) Compute $A = 0111 (7) - B = 0010 (2)$ with $S_{s u b} = 1$ .

Forecast: recall $S_{s u b} = 1$ means "flip $B$ to $\overline{B}$ and set $c_{0} = 1$ ", giving $A + \overline{B} + 1 = A - B$ . Predict the result and the meaning of $C$ .

Flip every bit of $B$ and force $c_{0} = 1$ . Why this step? In two's complement, negating means "invert all bits, add 1"; the ALU sneaks the " $+ 1$ " in as the carry-in so no extra adder is needed.
- $\overline{B} = \overline{0010} = 1101$ , and $c_{0} = 1$ .
Add $A + \overline{B} + 1$ . Why this step? Subtraction is literally this addition — running it column by column lets us read every carry, which the flags depend on.
- bit0: $1 + 1 + 1 = 11$ → $F_{0} = 1$ , $c_{1} = 1$
- bit1: $1 + 0 + 1 = 10$ → $F_{1} = 0$ , $c_{2} = 1$
- bit2: $1 + 1 + 1 = 11$ → $F_{2} = 1$ , $c_{3} = 1$
- bit3: $0 + 1 + 1 = 10$ → $F_{3} = 0$ , $c_{4} = 1$
Result $F = 0101 (5)$ .
Read the flags. Why this step? We must translate the raw carry $c_{4}$ into its subtraction meaning (borrow vs. no borrow), which is the whole reason to check $C$ here.
- $Z = 0$ , $C = c_{4} = 1$ , $N = 0$ , $V = c_{4} \oplus c_{3} = 1 \oplus 1 = 0$ .

Verify: $7 - 2 = 5$ ✓. Result non-negative → $C = 1$ means no borrow (grade-school subtraction would not have needed to borrow past the top). No signed overflow ( $V = 0$ ) since $5 \in [- 8, 7]$ . ✓

Worked example Example 5 — Cell #5: Subtract,

negative result ( $A < B$ ) Compute $A = 0010 (2) - B = 0101 (5)$ , $S_{s u b} = 1$ .

Forecast: $2 - 5 = - 3$ . How does a 4-bit box show $- 3$ ? And does $C$ go to 0 or 1?

Negate $B$ : invert to $\overline{B}$ and set $c_{0} = 1$ . Why this step? Same subtraction trick; we are really computing $2 + (- 5)$ .
- $\overline{B} = \overline{0101} = 1010$ , $c_{0} = 1$ .
Add $A + \overline{B} + 1$ . Why this step? Walking the columns exposes $c_{3}$ and $c_{4}$ , which we need to read $C$ and $V$ .
- bit0: $0 + 0 + 1 = 1$ → $F_{0} = 1$ , $c_{1} = 0$
- bit1: $1 + 1 + 0 = 10$ → $F_{1} = 0$ , $c_{2} = 1$
- bit2: $0 + 0 + 1 = 1$ → $F_{2} = 1$ , $c_{3} = 0$
- bit3: $0 + 1 + 0 = 1$ → $F_{3} = 1$ , $c_{4} = 0$
Result $F = 1101$ .
Read the flags. Why this step? A negative result must be recognised as negative — that is exactly what $N$ reports — and we must confirm $C$ signals the expected borrow.
- $Z = 0$ , $C = c_{4} = 0$ , $N = F_{3} = 1$ , $V = c_{4} \oplus c_{3} = 0 \oplus 0 = 0$ .

Verify: two's-complement $1101$ = $- (0010 + 1) = - (0011) = - 3$ ✓ (invert $1101 \to 0010$ , add 1 $\to 0011 = 3$ , so the value is $- 3$ ). $N = 1$ correctly flags a negative result. $C = 0$ means a borrow happened (as it must when $A < B$ ). $V = 0$ : $- 3$ is safely in range, no signed overflow. ✓

Worked example Example 6 — Cell #6: The

zero / degenerate case ( $A = B$ ) Compute $A = 0110 (6) - B = 0110 (6)$ , $S_{s u b} = 1$ . Subtracting a number from itself is the classic degenerate input.

Forecast: the result is obviously $0$ — but which of the four flags fire, and why?

Negate $B$ to $\overline{B}$ and add. Why this step? Confirms the ALU handles $A - A$ without special-casing it.
- $\overline{B} = \overline{0110} = 1001$ , $c_{0} = 1$ .
- bit0: $0 + 1 + 1 = 10$ → $F_{0} = 0$ , $c_{1} = 1$
- bit1: $1 + 0 + 1 = 10$ → $F_{1} = 0$ , $c_{2} = 1$
- bit2: $1 + 0 + 1 = 10$ → $F_{2} = 0$ , $c_{3} = 1$
- bit3: $0 + 1 + 1 = 10$ → $F_{3} = 0$ , $c_{4} = 1$
Result $F = 0000$ .
Read the flags. Why this step? This case exists to show how a CPU tests equality — it subtracts and inspects $Z$ — so reading $Z$ is the whole payoff.
- $Z = 1$ (the whole point), $C = c_{4} = 1$ (no borrow, since $A - A \geq 0$ ), $N = 0$ , $V = c_{4} \oplus c_{3} = 1 \oplus 1 = 0$ .

Verify: $6 - 6 = 0$ ✓. This is exactly how a CMP (compare) instruction works: it subtracts and only looks at the flags. $Z = 1$ ⇒ "equal". ✓

Worked example Example 7 — Cell #7: The

logic operations AND, OR, XOR (carries do not exist here) Using $A = 1100$ and $B = 1010$ , compute all three bitwise logic results the ALU offers, then decide which flags are even meaningful.

Forecast: logic works bit-by-bit and independently. Predict $A \land B$ , $A \lor B$ , $A \oplus B$ and which flags matter.

AND each column: output 1 only if both input bits are 1. Why this step? AND is the "both true" gate; running it per column shows the logic unit needs no carry chain at all.
- bit3: $1&1 = 1$ , bit2: $1&0 = 0$ , bit1: $0&1 = 0$ , bit0: $0&0 = 0$ → $A \land B = 1000$ .
OR each column: output 1 if either input bit is 1. Why this step? OR is the "at least one true" gate; like AND, each column is solved on its own, in parallel, instantly.
- bit3: $1∣1 = 1$ , bit2: $1∣0 = 1$ , bit1: $0∣1 = 1$ , bit0: $0∣0 = 0$ → $A \lor B = 1110$ .
XOR each column: output 1 when the two bits differ. Why this step? XOR is the "different" gate — the same $\oplus$ we use for the sum bit — and it completes the trio the logic unit provides.
- bit3: $1 \oplus 1 = 0$ , bit2: $1 \oplus 0 = 1$ , bit1: $0 \oplus 1 = 1$ , bit0: $0 \oplus 0 = 0$ → $A \oplus B = 0110$ .
Decide which flags mean anything. Why this step? Reporting a carry for an operation that never added would be nonsense — so we must consciously mark $C, V$ as invalid for all three results.
- For AND ( $1000$ ): $Z = 0$ , $N = 1$ . For OR ( $1110$ ): $Z = 0$ , $N = 1$ . For XOR ( $0110$ ): $Z = 0$ , $N = 0$ .
- There is no $c_{4}$ in any logic op — no addition happened — so $C$ and $V$ are meaningless and CPUs typically leave them untouched or clear them.

Verify: apply the truth tables per bit: AND $= 1000$ , OR $= 1110$ , XOR $= 0110$ ✓. Only $Z$ ("is it zero?") and $N$ ("is the top bit set?") make sense for pure logic. ✓

Worked example Example 8 — Cell #8: Real-world word problem (unsigned wrap-around)

A tiny thermostat stores temperature as an unsigned 4-bit value ( $0 \dots 15$ °C). It currently reads $13$ °C ( $1101$ ) and the sun adds $5$ °C. What does the display show, and does the chip know something went wrong?

Forecast: $13 + 5 = 18$ , but the display only holds $0 \dots 15$ . What number appears, and which flag lets the firmware notice the mistake?

Add $1101 + 0101$ , $S_{s u b} = 0$ . Why this step? This is unsigned addition — the ALU is identical to the signed case; only our interpretation of the bits differs.
- bit0: $1 + 1 + 0 = 10$ → $F_{0} = 0$ , $c_{1} = 1$
- bit1: $0 + 0 + 1 = 1$ → $F_{1} = 1$ , $c_{2} = 0$
- bit2: $1 + 1 + 0 = 10$ → $F_{2} = 0$ , $c_{3} = 1$
- bit3: $1 + 0 + 1 = 10$ → $F_{3} = 1$ , $c_{4} = 1$
Result $F = 0010 (2)$ .
Read the Carry flag. Why this step? For unsigned math, $C$ is the only signal that the true answer overflowed the 4-bit box — so the firmware must inspect exactly this bit, not $V$ .
- $C = c_{4} = 1$ (and $Z = 0$ , $N = F_{3} = 0$ ; $V = c_{4} \oplus c_{3} = 1 \oplus 1 = 0$ but $V$ is irrelevant for unsigned).

Verify: true sum $13 + 5 = 18$ ; kept in 4 bits, $18 - 16 = 2$ , matching $0010$ ✓. The display would wrongly read $2$ °C, but $C = 1$ lets the firmware detect the wrap-around and clamp the reading to $15$ °C. This is why watching $C$ matters in the real world. ✓

Worked example Example 9 — Cell #9: The exam twist (same bits, two answers)

An exam gives you the addition $1010 + 0110$ and asks: "State the result and interpret it (a) as unsigned and (b) as signed two's complement, and give $C$ and $V$ ."

Forecast: the bits have one answer, but the meaning splits in two. Predict both.

Add once — bits do not care about interpretation. Why this step? The ALU produces one bit pattern; interpretation is a human/compiler choice layered on top.
- bit0: $0 + 0 + 0 = 0$ → $F_{0} = 0$ , $c_{1} = 0$
- bit1: $1 + 1 + 0 = 10$ → $F_{1} = 0$ , $c_{2} = 1$
- bit2: $0 + 1 + 1 = 10$ → $F_{2} = 0$ , $c_{3} = 1$
- bit3: $1 + 0 + 1 = 10$ → $F_{3} = 0$ , $c_{4} = 1$
Result $F = 0000$ , with $c_{3} = 1$ , $c_{4} = 1$ .
Read the flags. Why this step? The exam explicitly asks for $C$ and $V$ ; computing both lets us show they can disagree.
- $Z = 1$ , $C = c_{4} = 1$ , $N = 0$ , $V = c_{4} \oplus c_{3} = 1 \oplus 1 = 0$ .
Give the two interpretations. Why this step? This is the trap: students report one number, but the same bits mean different values under the two conventions.
- Unsigned: $1010 = 10$ , $0110 = 6$ , $10 + 6 = 16$ . Held in 4 bits that is $0$ , and $C = 1$ flags the lost $16$ . So "unsigned $0$ with carry".
- Signed: $1010 = - 6$ , $0110 = + 6$ , $(- 6) + 6 = 0$ . Perfectly in range, so $V = 0$ — no signed overflow, even though $C = 1$ . The result $0$ is genuinely correct as a signed number.

Verify: both readings land on the bits $0000$ ✓; $C = 1$ (unsigned overflow) yet $V = 0$ (signed fine) — the cleanest possible demonstration that $C$ and $V$ answer different questions. ✓

Active Recall

Recall One flag per scenario — can you match them?

Which single flag is the "headline" for each cell? Add fits (Ex1) ::: none fire — the plain, happy case Add signed overflow (Ex2) ::: $V = 1$ (with $C = 0$ ) — carries into/out of sign bit disagree Add unsigned carry (Ex3) ::: $C = 1$ with $V = 0$ — a 5th bit fell off but the signed sum still fit Subtract, $A > B$ (Ex4) ::: $C = 1$ meaning no borrow Subtract, $A < B$ (Ex5) ::: $N = 1$ (negative) and $C = 0$ (borrow) $A - A$ (Ex6) ::: $Z = 1$ — the basis of the compare/equality test Logic AND/OR/XOR (Ex7) ::: only $Z, N$ are meaningful; $C, V$ ignored

Connections

Full Adder — the per-column adder every example above steps through
Two's Complement — why $\overline{B} + 1$ negates, used in Ex 4, 5, 6, 9
Multiplexer — routes the logic result in Ex 7
Status Flags and Condition Codes — how $Z, C, N, V$ drive branches
Ripple Carry Adder — the carry chain we traced bit by bit
Carry Lookahead Adder — a faster way to get the same carries
Datapath and Control Unit — where these operations get sequenced

Worked examples — ALU design fundamentals

The scenario matrix

The worked examples

Active Recall

Connections

Concept Map