3.3.13 · D5Combinational Circuits
Question bank — ALU design fundamentals
True or false — justify
The ALU stores the result of the last operation so the CPU can reuse it.
False. The ALU is purely combinational — output depends only on the current . The register file outside the ALU holds past results; the ALU has no clock.
Because subtraction and addition share the same adder, they take different amounts of time.
False. Both go through the identical carry chain; is set up by XOR gates and the line, which add no extra ripple stages. Same latency.
The Carry flag and the Overflow flag can never both be 1 at the same time.
False. They are computed independently (, ). Adding two large negative two's-complement numbers can set and simultaneously.
For a bitwise AND operation the Overflow flag is guaranteed to be 0.
False in meaning — it is simply undefined/meaningless. Logic ops don't run through the carry chain, so are garbage; software must ignore (and ) after logic ops.
In a two's-complement subtractor, means a borrow occurred.
False. means no borrow (result non-negative). The borrow flag is ; many CPUs invert the carry to report borrow.
The Zero flag can be read off a single result bit.
False. is the NOR of all result bits: . Every bit must be 0, so you need a wide OR/NOR, not one wire.
Adding a new operation (say, "min") to the ALU forces you to redesign the adder.
False. You add the new op's own combinational block in parallel and route it to one more Multiplexer input. The adder is untouched — that's the whole point of "compute all, then select".
The Sign flag being 1 always means the true mathematical answer is negative.
False. just copies the MSB. If overflow occurred (), the sign bit is corrupted, so can lie — e.g. shows though is positive.
Spot the error
" gives the sum bit of a full adder."
Wrong operator. Sum is parity: . AND () would give 1 only when all three are 1, missing the odd-count cases.
"To subtract, XOR with but leave ."
Missing the . Two's complement negation is ; the comes from feeding . With you'd compute , which is .
"Overflow is , the carry out of the top bit."
That's the Carry flag, not overflow. Signed overflow is — carry into vs out of the sign bit disagreeing.
"The MUX picks which operation to run, so unused units stay idle."
The units all run in parallel every cycle. The Multiplexer only routes one already-computed result to ; nothing is switched off.
" in two's complement."
Off by one. is the one's complement (). Correct is ; the extra 1 makes it true negation.
Why questions
Why does XOR, and not AND or OR, produce the sum bit?
Because the sum bit must be 1 exactly when an odd number of the three inputs is 1 — that is the definition of parity, which XOR computes.
Why can one control line turn an adder into a subtractor?
It does double duty: XORing inverts it, and the same bit fed as supplies the . Together that is , so .
Why is the ALU deliberately built with no clock inside?
Because it is combinational — its job is to give the correct output as soon as inputs settle. Timing/storage is delegated to clocked registers in the Datapath and Control Unit, keeping the ALU simple and fast.
Why does signed overflow correspond to ?
When the carry into the sign bit differs from the carry out, the sign bit flips for the wrong reason — two same-sign inputs produce an opposite-sign result, which is exactly signed overflow.
Why do we compute every operation in parallel instead of only the selected one?
Selecting before computing would need a decoder feeding inputs and would serialize the design. Computing all then MUX-ing is cheaper in gates-vs-speed and makes the datapath uniform.
Why is interpreted as "no borrow" in subtraction rather than "carry happened"?
Subtraction is really . If the sum overflows out of the top bit (), the true difference was non-negative — nothing had to be borrowed from beyond the MSB.
Edge cases
What are all flags for , addition (4-bit)?
, so , , , . The all-zero degenerate case sets only the Zero flag.
Subtracting a number from itself, : what should the flags say?
so ; and (no borrow), , . Any equal operands give zero and set , which is how a compare-for-equality branch works.
What happens when you add the two most-negative 4-bit numbers, ?
; low 4 bits . , but : signed overflow, since can't fit in .
Can the Zero flag be 1 while an overflow also occurred?
Yes. E.g. gives and : the true answer is nonzero, but the wrapped 4-bit result is , so misreports and warns you.
What flags are trustworthy after a bitwise OR operation?
Only and (they read the actual result bits). and are meaningless because logic ops bypass the carry chain — treat them as undefined.
For unsigned interpretation only, which single flag detects "the answer didn't fit"?
The Carry flag . Ignore entirely — only matters when bits are read as two's-complement signed values.
At the widest ALU width, does the overflow formula still hold?
Yes — it depends only on the two carries surrounding the sign bit, independent of . It works identically whether the adder is a Ripple Carry Adder or a Carry Lookahead Adder.
Connections
- Full Adder — the parity/majority logic these traps probe
- Two's Complement — source of the subtraction trick
- Multiplexer — the "compute all, then select" mechanism
- Status Flags and Condition Codes — Z, C, N, V meaning and misuse
- Ripple Carry Adder / Carry Lookahead Adder — same flag rules, different speed
- Datapath and Control Unit — where the clock and registers live, not the ALU