Intuition The ONE core ideaAn ALU is a single box that quietly computes every operation (add, subtract, AND, OR…) at the same time, then lets a tiny switch pick the one answer you asked for. Everything in the parent note is just spelling out how that "compute-everything-then-pick" box is wired from single-bit gates.
Before you can read the parent note, you must be able to read its language . Below is every symbol and idea it silently assumes, built in the order that each one leans on the one before it. Start at line one — nothing is assumed.
A bit is one wire that is either 0 (low voltage, "off") or 1 (high voltage, "on"). That is the entire alphabet of the hardware — no other symbols exist inside a chip.
To hold bigger numbers we put several bits side by side . Reading them like ordinary place-value digits — but with powers of 2 instead of 10 — gives a whole number.
n n b n − 1 … b 1 b 0 b 0 2 0 = 1 2 1 = 2 2 2 = 4 value = ∑ i = 0 n − 1 b i 2 i
The big Σ i 0 n − 1 b 0 2 0 + b 1 2 1 + …
0101 0 , 1 , 0 , 1 b 3 b 2 b 1 b 0 = 0101 0 ⋅ 8 + 1 ⋅ 4 + 0 ⋅ 2 + 1 ⋅ 1 = 5 A = 0101 ( 5 ) ( 5 )
A B F A B n into the ALU; F n out . A subscript picks one bit out of the bundle: A 2 A 2 2 A n − 1 most-significant bit (MSB) — worth the most; A 0 least-significant bit (LSB) .
Intuition Why bundle bits into letters?A 4-bit ALU has dozens of wires. Instead of naming each one, we say "A A i
A_i reveal checkbit number i A 2 i
The parent note writes formulas like a i ⊕ b i ⊕ c i logic gates — tiny circuits that take 0/1 inputs and give a 0/1 output. Here is each one, its rule, and its picture.
Definition The four gate symbols
AND — written as a dot a ⋅ b ab only if both inputs are 1. Think: both switches closed. OR — written a + b at least one input is 1. (This + not arithmetic plus — context tells them apart.)XOR — written a ⊕ b differ (exactly one is 1). "eXclusive OR."NOT — written with a bar, a 0 = 1 1 = 0
Intuition Why XOR is the "odd-count / difference" gateLook at its truth table: it fires only when the two inputs disagree. Chain three of them, a ⊕ b ⊕ c odd number of the three inputs are 1. That "parity" behaviour is precisely what a sum bit needs (see §5), which is why the parent note reaches for XOR and not AND.
a + b Why it feels right: + The fix: inside a logic expression + OR (1 + 1 = 1 2
a ⊕ b reveal checkXOR — outputs 1 when the two inputs differ.
The bar over B NOT — flip every bit of B
When you add digits, sometimes a column overflows into the next — that spill is the carry . In decimal, 7 + 5 = 12 1 + 1 = 10
c i coming into bit position i c 0 c n out of the top bit — it "falls off the end" and becomes the Carry flag.
Intuition Why carries must chainBit 0 can't finish until it hands its carry to bit 1, which hands to bit 2… This left-flowing chain is the whole reason a Ripple Carry Adder exists — and why a Carry Lookahead Adder tries to compute the carries early instead of waiting.
The parent's magic line is A − B = A + B + 1
Definition Two's complementTo represent − x n x x negative weight − 2 n − 1 + 2 n − 1
So a 4-bit pattern's signed value is
value = − b 3 ⋅ 2 3 + b 2 ⋅ 2 2 + b 1 ⋅ 2 1 + b 0 ⋅ 2 0 [ − 8 , 7 ] why Example 1 in the parent overflows.
Worked example Negating 2 in 4 bits2 = 0010 1101 1110 1110 = − 8 + 4 + 2 = − 2 Two's Complement for the full story.
Intuition Why flip-and-add-one gives subtractionIf B + 1 is − B A + B + 1 is A + ( − B ) = A − B B c 0
Negate x in two's complement reveal checkflip every bit (x
Now every symbol in the parent's core equations is defined, so they read like plain English:
Definition Multiplexer (MUX)A multiplexer is a switch: it has several data inputs, a few select lines S one output. The number on S k 2 k
Intuition Why the ALU needs a MUXThe adder and the logic gates all run at once — every answer exists simultaneously on separate wires. The MUX is the little switch that points at the drawer you asked for and hands you that one answer. That is the "compute-everything-then-pick" idea from the very top. Full details in Multiplexer .
The bundle of select lines is the S F = MUX ( S , … ) Datapath and Control Unit .
The parent produces four extra one-bit outputs that describe the result. Now that carries and the MSB are defined, each is readable:
Naming wires A B F subscripts
Multiplexer picks one result
Read a 4-bit pattern like 0110 0 ⋅ 8 + 1 ⋅ 4 + 1 ⋅ 2 + 0 ⋅ 1 = 6
State the rule for AND, OR, XOR, NOT AND=1 iff both 1; OR=1 iff at least one 1; XOR=1 iff they differ; NOT flips the bit.
Explain why a ⊕ b ⊕ c XOR outputs 1 when an odd number of inputs are 1 — exactly what a sum column needs.
Negate a number in two's complement flip every bit then add 1 (x + 1
Say what c 0 c n c 0 c n
Explain what a multiplexer does routes one of several inputs to a single output, chosen by the select lines S
Tell C V C V = c n ⊕ c n − 1
Interpret the MSB F n − 1 unsigned: worth + 2 n − 1 − 2 n − 1