Decoders (2 - 4, 3 - 8): Worked examples — Hardware deep dive

This page is the "case gym" for the parent decoder note. We take every kind of question a decoder can throw at you and grind through one worked example per case — from the simplest "which line lights up" to active-low chips, demux routing, and full chip-expansion. Read the scenario matrix first, then work each example before peeking at the steps.

Everything here is built on one fact you already met: a decoder turns a binary address (a number written in 0s and 1s) into a one-hot output — exactly one wire goes "hot" (active), the one whose number equals the address. If any word here is unfamiliar, that's fine — each example rebuilds it from zero.

The scenario matrix

Every decoder problem is one of these case classes. The examples below each carry a tag like (Cell A) so you can see the whole grid is covered.

Cell	Case class	What makes it tricky	Covered by
A	Plain 2:4 evaluate	mapping binary → decimal index	Ex 1
B	Plain 3:8 evaluate	3 bits, bigger index arithmetic	Ex 2
C	MSB/LSB swap trap	reading bits in the wrong order	Ex 3
D	Disabled chip (Enable = 0)	the degenerate all-zero output	Ex 4
E	Active-low outputs	"selected" means 0, not 1	Ex 5
F	Implement an SOP function	OR the right minterm outputs	Ex 6
G	Decoder as demultiplexer	data on Enable, routing	Ex 7
H	Limiting / boundary cases	address 0, address $2^{n} - 1$	Ex 8
I	Real-world word problem	memory row/chip select	Ex 9
J	Exam twist (build 4:16)	hierarchical expansion	Ex 10

Setup: labels we will reuse

Before any symbol appears in an example, here is the full vocabulary, once. Nothing below this box uses a symbol not defined here.

Definition Enable pin

$E$ — one master switch on every output Real decoders add one extra input, the Enable pin, written $E$ . It is a master on/off switch that is wired into every output through an AND gate, so each output becomes $D_{k} = E \cdot m_{k} .$ Read $E \cdot m_{k}$ as " $E$ AND $m_{k}$ ": the output is 1 only when both $E = 1$ and the minterm $m_{k} = 1$ .

Active-high enable: $E = 1$ → chip works normally; $E = 0$ → all outputs off (the degenerate state), because $0 \cdot (anything) = 0$ .
Active-low enable: written $\overline{E}$ ; the chip is on when $\overline{E} = 0$ and off when $\overline{E} = 1$ . Do not assume "enable" always means active-high — always check the chip's bubbles.

The tiny truth table below shows the wrapper behaviour on one representative output $D_{2}$ of a 2:4 decoder (so $m_{2} = A_{1} \overline{A_{0}}$ ). Notice the whole " $m_{2}$ " column is ignored whenever $E = 0$ :

$E$	$A_{1}$	$A_{0}$	$m_{2} = A_{1} \overline{A_{0}}$	$D_{2} = E \cdot m_{2}$
0	1	0	1	0 (chip asleep)
0	0	1	0	0
1	1	0	1	1 (selected)
1	0	1	0	0

Every other output ( $D_{0}, D_{1}, D_{3}$ ) has the identical wrapper — only its minterm differs.

Worked Examples

Ex 1 — Plain 2:4 evaluate (Cell A)

Reading the figure. The box is the decoder; the two arrows on the left are the input bits $A_{1} = 0, A_{0} = 1$ ; the four arrows on the right are $D_{0} \dots D_{3}$ . Three are grey (logic 0) and one is red — that red wire is $D_{1}$ . It maps directly to step 3: the algebra said " $D_{1} = m_{1} = \overline{A_{1}} A_{0} = 1$ ", and the picture shows exactly that one wire carrying current while its three siblings stay dark.

Ex 2 — Plain 3:8 evaluate (Cell B)

Ex 3 — MSB/LSB swap trap (Cell C)

Worked example

Same 3:8 decoder. A student reads the input "left to right" as $A_{0} A_{1} A_{2} = 011$ but the physical wiring is $A_{2} A_{1} A_{0}$ . The actual electrical inputs are $A_{2} = 1, A_{1} = 1, A_{0} = 0$ . What output truly fires, and what wrong answer does the student get?

Forecast: Two different answers — predict both.

Student's (wrong) reading. They treat the string as value $01 1_{2} = 3$ , so they claim $D_{3}$ . Why this step? This is the classic error: reading bits without matching them to weights.
Correct reading by weight. Actual bits $A_{2} A_{1} A_{0} = 110$ . Value $= 1 \cdot 4 + 1 \cdot 2 + 0 \cdot 1 = 6$ . Why this step? Only the MSB-anchored weighting gives the real hardware answer.
Result. The true hot line is $D_{6}$ , not $D_{3}$ .

Verify: $D_{6} = m_{6} = A_{2} A_{1} \overline{A_{0}} = 1 \cdot 1 \cdot \overline{0} = 1$ . ✓ The wrong $D_{3} = m_{3} = \overline{A_{2}} A_{1} A_{0} = \overline{1} \cdot 1 \cdot 0 = 0$ — off, confirming the student would light the wrong lamp. ✓

Reading the figure. The single bit-string "0 1 1" sits at the top. Two arrows fan out: the grey left branch is the wrong reading (bits taken as $A_{0} A_{1} A_{2}$ , giving value 3 → grey $D_{3}$ lamp), and the red right branch is the correct MSB-anchored reading (bits as $A_{2} A_{1} A_{0} = 110$ , giving value 6 → red $D_{6}$ lamp). The picture shows the two branches landing on different lamps — a direct visual of step 3's " $D_{6}$ , not $D_{3}$ ".

Ex 4 — Disabled chip: the degenerate case (Cell D)

Ex 5 — Active-low outputs, multi-enable chip (Cell E)

Worked example

A 74138-style 3:8 decoder has active-low outputs and three enable pins $\overline{E_{1}}, \overline{E_{2}}, E_{3}$ (defined in the "several enable pins" box above). Its pins are set to $\overline{E_{1}} = 0, \overline{E_{2}} = 0, E_{3} = 1$ . Given address $A_{2} A_{1} A_{0} = 101$ , what value appears on each output line?

Forecast: In active-low logic, "selected" is the odd one out. Predict which line differs from the rest.

Combine the enable pins. $E_{eff} = \overline{E_{1}} = 0 AND \overline{E_{2}} = 0 AND E_{3} = 1 = 1$ → the chip is on. Why this step? With several enables the chip works only when all agree; if any one disagreed, $E_{eff} = 0$ and every output would sit inactive (all 1s here). Never assume enable is active-high.
Find the selected index. $10 1_{2} = 1 \cdot 4 + 0 \cdot 2 + 1 \cdot 1 = 5$ . So line 5 is selected. Why this step? Selection arithmetic is identical to active-high — only the output level changes.
Assign active-low levels. The selected line goes to 0; all others sit at 1 (recall the bar notation: $\overline{D_{k}} = 0$ means "line $k$ selected"). Why this step? "Active-low output" means the asserted (chosen) state is a logic 0.
Result. $\overline{D_{5}} = 0$ ; $\overline{D_{0}} = \overline{D_{1}} = \overline{D_{2}} = \overline{D_{3}} = \overline{D_{4}} = \overline{D_{6}} = \overline{D_{7}} = 1$ .

Verify: Number of lines at 0 must be exactly one → count = 1. ✓ The index of that 0 equals the decimal address $5$ . ✓ (If you ever see all lines at 1, the chip is disabled — the active-low all-off state.)

Reading the figure. Eight output arrows leave the box. Seven are grey and labelled "1" (their inactive level), and the single red arrow is labelled "0" — that lonely 0 is the selected line $\overline{D_{5}}$ . This is the visual of step 3: active-low flips the meaning, so the winner is the one wire at 0 while all its siblings rest at 1.

Ex 6 — Implement an SOP function (Cell F)

Worked example

Using a 3:8 decoder (active-high) plus one OR gate, implement $F (A, B, C) = \sum m (2, 3, 5) .$ Which decoder outputs do you OR, and what is $F$ when $A B C = 010$ ?

Forecast: How many wires enter the OR gate?

Map variables to inputs. Let $A = A_{2}$ , $B = A_{1}$ , $C = A_{0}$ . Why this step? The decoder produces every minterm $m_{0} \dots m_{7}$ on its output lines ( $D_{k} = m_{k}$ ); we just pick the ones we want. Ordering the variables fixes which output is which minterm.
Pick the outputs. $\sum m (2, 3, 5)$ (the OR of minterms 2, 3, 5) means OR together $D_{2}, D_{3}, D_{5}$ : $F = D_{2} + D_{3} + D_{5} .$ Why this step? A sum-of-minterms is 1 exactly when the input matches one of those minterms — and each $D_{k}$ is already that minterm.
Evaluate at $A B C = 010$ . Value $= 0 \cdot 4 + 1 \cdot 2 + 0 \cdot 1 = 2$ , so $D_{2} = 1$ , hence $F = 1$ . Why this step? Input 2 is in the set ${2, 3, 5}$ , so $F$ must be 1.

Verify: Truth-check the full set. $F = 1$ for inputs ${2, 3, 5}$ and $0$ otherwise. At input $4$ : $D_{2} = D_{3} = D_{5} = 0 \Rightarrow F = 0$ . ✓ At input $3$ : $D_{3} = 1 \Rightarrow F = 1$ . ✓ Exactly three inputs give $F = 1$ . ✓

Ex 7 — Decoder as demultiplexer (Cell G)

Worked example

Take a 2:4 decoder and feed a data bit $x$ into the Enable pin $E$ instead of a constant. Address is $A_{1} A_{0} = 11$ . A stream sends $x = 1, 0, 1$ over three clock ticks. What appears on the outputs each tick?

Forecast: Which single output "carries" the data, and what do the rest do?

Recall the enabled form. $D_{k} = E \cdot m_{k}$ ; now $E = x$ is the data, not a fixed enable. Why this step? This turns the decoder into a demultiplexer: one input routed to one of $2^{n}$ outputs.
Find the routed line. $1 1_{2} = 3$ , so only $m_{3}$ is 1; every other minterm is 0. Why this step? The address selects which output copies $x$ .
Compute per tick. $D_{3} = x \cdot m_{3} = x \cdot 1 = x$ , so $D_{3}$ follows the stream $1, 0, 1$ . All others $= x \cdot 0 = 0$ always. Why this step? The unselected outputs are gated by a 0 minterm, so they stay 0 no matter what $x$ does.

Verify: Tick 1: $x = 1 \Rightarrow D_{3} = 1$ , others 0. ✓ Tick 2: $x = 0 \Rightarrow D_{3} = 0$ , others 0. ✓ Tick 3: $x = 1 \Rightarrow D_{3} = 1$ . ✓ The data appeared only on $D_{3}$ — routing achieved.

Ex 8 — Boundary / limiting cases (Cell H)

Worked example

For a 3:8 decoder, work the two extreme addresses: the smallest ( $A_{2} A_{1} A_{0} = 000$ ) and the largest ( $A_{2} A_{1} A_{0} = 111$ ). Which lines fire?

Forecast: Guess both endpoints.

Smallest address. $00 0_{2} = 0$ , so $D_{0}$ fires. Why this step? Zero is a valid address — it maps to line 0, the "all-complemented" minterm.
Its minterm. $D_{0} = m_{0} = \overline{A_{2}} \overline{A_{1}} \overline{A_{0}} = \overline{0} \cdot \overline{0} \cdot \overline{0} = 1 \cdot 1 \cdot 1 = 1$ . Why this step? All-zero input still selects exactly one line — never "no line" (unless disabled).
Largest address. $11 1_{2} = 4 + 2 + 1 = 7$ , so $D_{7}$ fires. Why this step? The top address maps to the last line, the "all-true" minterm.
Its minterm. $D_{7} = m_{7} = A_{2} A_{1} A_{0} = 1 \cdot 1 \cdot 1 = 1$ .

Verify: For an $n$ -input decoder the valid indices run $0$ to $2^{n} - 1$ . Here $n = 3 \Rightarrow 0 \dots 7$ , and our endpoints are exactly $0$ and $7$ . ✓ Both minterms evaluate to 1. ✓ There is no address that selects "no line" — only the disable pin can do that (Ex 4).

Ex 9 — Real-world: memory chip select (Cell I)

Worked example

A computer has 4 memory chips, each holding one block of addresses. Each chip has a Chip-Select (CS) pin — a control input that "wakes up" that chip so it can drive the data bus; while $C S$ is inactive the chip is silent. The CPU's two high address bits $A_{15} A_{14}$ pick which chip. Treat $C S$ as active-high here ( $C S = 1$ means selected). If $A_{15} A_{14} = 10$ , which chip's $C S$ should be asserted?

Forecast: Which of chips 0–3 wakes up?

Recognise the decoder. Two select bits → a 2:4 decoder whose four outputs are the four $C S$ lines $C S_{0} \dots C S_{3}$ . Why this step? Memory Address Decoding is literally "address bits in, one-hot chip-enable out."
Convert the select bits. $1 0_{2} = 1 \cdot 2 + 0 \cdot 1 = 2$ . Why this step? The decimal value is the chip index to enable.
Assert that CS. $C S_{2}$ is asserted (=1); $C S_{0}, C S_{1}, C S_{3}$ stay inactive (=0). Why this step? One-hot guarantees only one chip drives the data bus — no bus conflict. (On real RAM the $C S$ is often active-low, $\overline{C S}$ ; then "selected" would be 0 — same idea, flipped polarity.)

Verify: $C S_{2} = m_{2} = A_{15} \overline{A_{14}} = 1 \cdot \overline{0} = 1$ (active); $C S_{0} = m_{0} = \overline{A_{15}} \overline{A_{14}} = 0$ . ✓ Exactly one chip enabled — this is why decoders prevent two chips fighting over the same wires. ✓

Ex 10 — Exam twist: build a 4:16 decoder (Cell J)

Worked example

Build a 4:16 decoder from two 3:8 decoders (each with an active-high enable $E$ ). Inputs $A_{3} A_{2} A_{1} A_{0}$ . For input $A_{3} A_{2} A_{1} A_{0} = 1011$ , which of the 16 outputs fires, and which sub-decoder is enabled?

Forecast: Which decoder wakes, and which line?

Split the bits. MSB $A_{3}$ chooses the decoder; the lower three bits $A_{2} A_{1} A_{0}$ address inside it. Why this step? Same hierarchical trick as building 3:8 from two 2:4 — the top bit selects a "bank."
Wire the enables. Top 3:8 (outputs $D_{0} \dots D_{7}$ ) enabled by $E = \overline{A_{3}}$ ; bottom 3:8 (outputs $D_{8} \dots D_{15}$ ) enabled by $E = A_{3}$ . Why this step? $A_{3}$ and $\overline{A_{3}}$ are opposites, so exactly one bank is ever enabled (the other sits in Ex 4's all-off state).
Evaluate the enables for this input. $A_{3} = 1$ → bottom enable $E = A_{3} = 1$ (on), top enable $E = \overline{A_{3}} = 0$ (off). Why this step? Only the on-bank can produce a hot line; the off-bank contributes all zeros.
Address inside the on-bank. Lower bits $A_{2} A_{1} A_{0} = 011 = 3$ → the bottom decoder fires its line 3. Why this step? Inside the enabled bank, ordinary 3:8 selection (weigh-and-add) applies.
Convert to a global index. The bottom bank's outputs are numbered $D_{8} \dots D_{15}$ , so its internal line 3 is global $D_{8 + 3} = D_{11}$ . Why this step? We must translate the sub-decoder's local index into the 4:16's global numbering.
Result. The single hot output is $D_{11}$ ; all other 15 outputs are 0.

Verify: Compute the full-address decimal directly: $101 1_{2} = 1 \cdot 8 + 0 \cdot 4 + 1 \cdot 2 + 1 \cdot 1 = 11$ , which matches $D_{11}$ . ✓ Top decoder disabled ( $\overline{A_{3}} = 0$ ) so $D_{0} \dots D_{7}$ are all 0. ✓ Exactly one of 16 lines hot — a valid one-hot output. ✓

Reading the figure. Two stacked boxes are the two 3:8 banks. The red wire from $A_{3}$ is the steering signal: it feeds $\overline{A_{3}} = 0$ to the top box (drawn grey = the off / all-zero bank of step 3) and $A_{3} = 1$ to the bottom box (drawn black = on). Inside the live bottom bank the lower bits pick internal line 3, which the numbering maps to the red output $D_{11}$ on the right — mirroring steps 3→5 exactly.

Recall

Recall Which cell is which?

Cell D (disabled) is the only case with ::: zero hot lines — every other case has exactly one.

Recall Active-low selected line

On an active-low chip the selected output is ::: 0, and all the others are 1.

Recall Decoder-as-demux

To make a decoder route a data bit, put the data on the ::: Enable pin; the address selects which output copies it.

Recall 4:16 from two 3:8

The extra top bit ( $A_{3}$ ) is used to ::: enable one 3:8 bank via $A_{3}$ / $\overline{A_{3}}$ while the lower three bits address inside it.

Recall What is a minterm

$m_{k}$ ? An AND of all inputs, complemented where the bit of $k$ is 0, that is 1 for ::: exactly one input combination — namely $k$ ; and $D_{k} = m_{k}$ .

Recall Multi-enable chip (74138)

A chip with pins $\overline{E_{1}}, \overline{E_{2}}, E_{3}$ is enabled only when ::: all agree: $\overline{E_{1}} = 0$ AND $\overline{E_{2}} = 0$ AND $E_{3} = 1$ .

Connections

Decoders (2 - 4, 3 - 8) — parent note; this page drills its every case.
Minterms and Maxterms — each output is a minterm (Ex 6).
Sum of Products (SOP) — decoder + OR realizes any SOP (Ex 6).
Demultiplexers — decoder + data-on-enable (Ex 7).
Multiplexers — complementary block.
Encoders — the inverse (one-hot in, binary out).
Memory Address Decoding — chip-select example (Ex 9).
7-Segment Display Driver — another decode-to-many use.

Worked examples — Decoders (2 - 4, 3 - 8)

The scenario matrix

Setup: labels we will reuse

Worked Examples

Ex 1 — Plain 2:4 evaluate (Cell A)

Ex 2 — Plain 3:8 evaluate (Cell B)

Ex 3 — MSB/LSB swap trap (Cell C)

Ex 4 — Disabled chip: the degenerate case (Cell D)

Ex 5 — Active-low outputs, multi-enable chip (Cell E)

Ex 6 — Implement an SOP function (Cell F)

Ex 7 — Decoder as demultiplexer (Cell G)

Ex 8 — Boundary / limiting cases (Cell H)

Ex 9 — Real-world: memory chip select (Cell I)

Ex 10 — Exam twist: build a 4:16 decoder (Cell J)

Recall

Connections

Case Map