Decoders (2 - 4, 3 - 8): Question bank — Hardware deep dive

Reminders used throughout (all built in the parent note):

Address = the binary number on the inputs; decimal value of that number = the index of the one output that goes hot.
One-hot = exactly one output active at a time.
Enable (E): active-high $E = 0$ silences the whole chip; active-low $\overset{ˉ}{E} = 1$ silences it. Watch which convention is stated.
Active-low output: the selected line reads $0$ , all others read $1$ (the inversion "bubble" on the datasheet).

True or false — justify

n : 2^{n}

decoder can have two outputs high at the same time.

False. By construction each output is a distinct minterm, and any input matches exactly one minterm — so at most one output is high (zero if the chip is disabled). "One-hot" is the whole point.

For every possible input, some decoder output is always high.

False. Only true when the chip is enabled. If the enable input is in its "off" state (

E = 0

for active-high enable), all outputs are inactive regardless of the address.

The input address

A_{1} A_{0} = 00

leaves all outputs at 0 because "zero means nothing selected."

False. Address

00

has decimal value

0

, so it selects

D_{0}

. Zero is a perfectly valid index;

D_{0} = \overline{A_{1}} \overline{A_{0}}

fires precisely here.

A 3:8 decoder has 3 inputs, so it can select among

3 \times 2 = 6

outputs.

False.

n

inputs give

2^{n}

outputs, not

2 n

. Three inputs →

2^{3} = 8

outputs. The count is exponential because binary combinations grow that way.

Simplifying decoder equations with a K-map reduces the number of gates.

False. Each output is a single minterm — there is nothing to combine. A K-map only helps when several 1's in a column can merge; a decoder column has exactly one 1, so no simplification exists.

Swapping which physical wire you call the MSB changes which output fires.

True. The MSB carries weight

2^{n - 1}

; the LSB carries weight

2^{0}

. Reading

A_{1} A_{0} = 10

as "2" versus "1" depends entirely on which wire is the MSB — get it backwards and you activate the wrong line.

A decoder and an encoder are the same block wired differently.

False. They are inverse functions, not the same hardware. Decoder: binary→one-hot (few→many). Encoder: one-hot→binary (many→few). You cannot rewire one into the other without different internal gates.

Putting a data bit on the enable pin turns the decoder into a demultiplexer.

True. The enable gates every output, so the selected line copies the data value while the rest stay at 0 — that is exactly routing one input to one of many outputs, the definition of a demux.

On a 74138-style active-low decoder, the selected line is at logic 1.

False. Active-low means the selected output is driven to 0, and all the others sit at 1. The inversion bubble on the datasheet is the tell.

Any Sum-of-Products function on 3 variables can be built with one 3:8 decoder and one OR gate.

True. The decoder already emits all eight minterms; OR-ing the ones present in the function gives

F

. (Some functions want a NOR / active-low OR, but one decoder + one gate suffices.)

Spot the error

D_{5} = A_{2} A_{1} \overline{A_{0}}

because

5 = 101

The pattern for

5 = 10 1_{2}

A_{2} = 1, A_{1} = 0, A_{0} = 1

, so

D_{5} = A_{2} \overline{A_{1}} A_{0}

. The stated term is

A_{2} A_{1} \overline{A_{0}}

, which is the pattern

110 = 6

— that's

D_{6}

, not

D_{5}

"With active-high enable,

D_{2} = A_{1} \overline{A_{0}} + E

Enable gates (multiplies) the minterm, it doesn't OR into it. The correct form is

D_{2} = E \cdot A_{1} \cdot \overline{A_{0}}

: when

E = 0

the product is 0 (silenced); adding

E

would force

D_{2} = 1

whenever the chip is enabled, breaking one-hot.

"To build a 3:8 from two 2:4s, enable both decoders all the time and feed

A_{1} A_{0}

to both."

If both are always enabled, both fire one line each → two outputs high → not one-hot. You must enable the top with

\overline{A_{2}}

and the bottom with

A_{2}

so exactly one decoder is awake per input.

F (A, B, C) = \sum m (1, 4, 7)

: wire

A = A_{0}, B = A_{1}, C = A_{2}

then OR

D_{1}, D_{4}, D_{7}

Minterm indices assume

A

is the MSB (

A_{2}

C

the LSB (

A_{0}

). Wiring

A

A_{0}

reverses the weights, so the minterm numbers shift and you OR the wrong outputs. Map MSB-to-MSB:

A \to A_{2}, B \to A_{1}, C \to A_{0}

"A decoder with no enable input is broken — it has no way to be turned off."

Not broken, just simpler. A bare decoder is always active and always drives exactly one output high; that is a complete, valid decoder. Enable is a convenience for cascading and demux use, not a requirement for correctness.

"For a 2:4 decoder, address 11 gives

D_{3}

and also weakly drives

D_{1}, D_{2}

since they share inputs."

Sharing input wires does not mean sharing output activation.

D_{3} = A_{1} A_{0}

is the only term that is 1 at

11

;

D_{1} = \overline{A_{1}} A_{0}

and

D_{2} = A_{1} \overline{A_{0}}

evaluate to 0 there. Logic is exact, not "weak."

Why questions

Why is each decoder output literally a minterm, with no simplification possible?

A minterm is the unique product term that equals 1 for exactly one input combination — which is exactly what each one-hot output needs. One row, one 1, one minterm: nothing to merge.

Why does the enable input let you build big decoders from small ones?

Enable lets a high-order address bit choose which sub-decoder is awake. Feeding the low bits to all sub-decoders and enabling exactly one via the high bit reconstructs a full one-hot over the larger output set.

Why do memory chips need a decoder rather than just using the binary address directly?

RAM needs a dedicated select wire per row/chip, but the address arrives as a compact binary number. The decoder bridges "compact number" to "one dedicated wire," activating exactly the addressed row. See Memory Address Decoding.

Why is putting the data bit on the enable pin equivalent to demultiplexing?

Enable multiplies every output. The addressed output is already 1 internally, so it becomes

1 \cdot data = data

; the others are 0. One data stream is thus routed to whichever output the address picks.

Why are active-low outputs common on real decoder ICs even though they feel backwards?

Open-collector / wired-AND buses and older TTL logic drive lines low more cleanly, and "select = pull low" composes naturally with active-low chip-select conventions in memory. It's a hardware-convention choice, not a logical necessity.

Why can't a decoder's outputs ever encode a number bigger than

2^{n} - 1

There are only

2^{n}

output lines and only

2^{n}

distinct input combinations. The largest index is

2^{n} - 1

(all inputs 1); no input pattern points beyond it.

Edge cases

Decoder is enabled, address = all zeros. What is the output state?

D_{0} = 1

, every other output

= 0

. All-zero address is index 0, a normal selection — not an "off" state.

Enable is off (active-high

E = 0

) but the address is a valid number like 3. Which output fires?

None. Enable overrides the address:

D_{k} = E \cdot m_{k} = 0 \cdot m_{k} = 0

for all

k

. The address is ignored while asleep.

A 1:2 "decoder" (n=1). Is that a real decoder, and what are its equations?

Yes — the smallest one. One input

A_{0}

, two outputs:

D_{0} = \overline{A_{0}}

D_{1} = A_{0}

. It is effectively a NOT gate plus a wire, and doubles as a 1-to-2 demux with enable.

Active-low decoder, chip disabled. What do all the output lines read?

All outputs sit at 1 (their inactive state). "No line selected" on an active-low part means everything is high — the mirror image of the active-high all-zeros case.

Two decoder outputs are wired together (tied) by mistake. What happens logically?

They can conflict: if one output tries to drive high and its neighbour low, you get a bus contention / undefined level on standard push-pull outputs. One-hot only holds per chip; tying outputs breaks the guarantee.

Feed a 3:8 decoder an address, but only the two LSBs are connected and the MSB floats. Which outputs can fire?

With the MSB undefined the selected index is unpredictable — it may land in either the low half (0–3) or high half (4–7). Floating inputs violate the "every input is a defined 0 or 1" premise, so the one-hot result is not guaranteed.

You OR together all outputs of an enabled decoder. What is the result?

Always 1 (when enabled), because exactly one output is high for every address, so the OR is never 0. This is a handy way to detect "chip is enabled and addressed."

Recall One-line self-test before you move on

Cover the answers: for each of "disabled chip," "all-zero address," and "active-low selected line," state the output pattern from memory. Disabled (active-high E) ::: all outputs 0. All-zero address, enabled ::: $D_{0} = 1$ , rest 0. Active-low, line 3 selected ::: $D_{3} = 0$ , all others 1.

Connections

Decoders (2 - 4, 3 - 8) — parent: the mechanism these traps test.
Minterms and Maxterms — every "why is it a minterm" item lives here.
Demultiplexers — the enable-as-data trap.
Encoders — the inverse-confusion trap.
Sum of Products (SOP) — the "one decoder + OR" claims.
Memory Address Decoding — the real-world "why not use binary directly" question.
Multiplexers — complementary block worth contrasting.
7-Segment Display Driver — a decoding application to sanity-check intuition.