Decoders (2 - 4, 3 - 8): Exercises — Hardware deep dive

Everything here builds on the parent note Decoders (2:4, 3:8). If a term feels unfamiliar, that note defines it from zero.

Reminder of the machinery we will reuse (every symbol earned before use):

Definition The four tools we lean on

$n$ : the number of address inputs a decoder has. An $n$ -input decoder has $2^{n}$ outputs (we call it an " $n : 2^{n}$ decoder"). So $n = 2$ gives a 2:4 decoder, $n = 3$ gives a 3:8 decoder, and so on. Whenever you see $n$ on this page, read it as "how many address wires go in".
Address: the binary number you feed in. In a 2-input decoder we call the inputs $A_{1}$ (the MSB = Most Significant Bit, the one worth $2$ ) and $A_{0}$ (the LSB = Least Significant Bit, worth $1$ ). The decimal value of the address is $2 A_{1} + A_{0}$ .
One-hot output: exactly one output wire is $1$ ; all the rest are $0$ . The wire that is hot is the one whose number equals the address's decimal value. We write output number $k$ as $D_{k}$ .
Minterm: an AND of every input, each input written either "as is" (true form, e.g. $A_{1}$ ) or "flipped" (complement form, written with a bar, e.g. $\overline{A_{1}}$ meaning NOT- $A_{1}$ ). A minterm equals $1$ for exactly one input combination. That is why each decoder output is a minterm — see Minterms and Maxterms.

One picture to carry the whole page. Before any exercise, look at how a binary address turns into one hot line. The arrows under each bit show its weight (what that bit is worth); you add only the weights above a $1$ , and the resulting number is the single output that lights up (shown in coral).

Level 1 — Recognition

Goal: can you read a decoder and state which line fires?

L1-Q1. A 2:4 decoder receives $A_{1} A_{0} = 01$ . Which output $D_{k}$ is high, and what are the other three?

L1-Q2. A 3:8 decoder receives $A_{2} A_{1} A_{0} = 011$ . Which single output is high?

L1-Q3. True or false: for a working 2:4 decoder it is possible for both $D_{1}$ and $D_{2}$ to be $1$ at the same time. Justify in one sentence.

Recall Solutions — Level 1

Use the weight picture at the top of the page (s02) as your worksheet — write the weights under the bits, then add only the columns showing a $1$ .

L1-Q1. Compute the decimal value of the address: $2 A_{1} + A_{0} = 2 (0) + 1 = 1$ . So the hot line is $D_{1} = 1$ , and $D_{0} = D_{2} = D_{3} = 0$ . Check with the minterm formula: $D_{1} = \overline{A_{1}} A_{0} = \overline{0} \cdot 1 = 1 \cdot 1 = 1$ . ✓

L1-Q2. Value $= 4 A_{2} + 2 A_{1} + A_{0} = 4 (0) + 2 (1) + 1 = 3$ . So $D_{3} = 1$ ; every other output is $0$ . Check: $01 1_{2} = 3$ , and $D_{3} = \overline{A_{2}} A_{1} A_{0} = \overline{0} \cdot 1 \cdot 1 = 1$ . ✓

L1-Q3. False. By definition the outputs are mutually-exclusive minterms — each is $1$ for exactly one distinct address, and one address cannot be two things at once. So exactly one output is hot, never two together. (Once we meet the enable pin in Level 2 we'll see there is also a "chip off" state where zero outputs are hot — but still never two.)

Level 2 — Application

Goal: use the formulas and the enable input correctly.

L2-Q1. Write the full Boolean expression for $D_{5}$ of a 3:8 decoder in true/complement form.

L2-Q2. A 2:4 decoder has an active-high enable $E$ . Its outputs are $D_{k} = E \cdot (minterm)$ . If $E = 0$ and $A_{1} A_{0} = 11$ , what is $D_{3}$ ? What if $E = 1$ with the same address?

L2-Q3. A commercial 74138-style chip has active-low outputs: the selected line goes to $0$ , all others stay $1$ . (The real 74138 also has three enable pins that must all be in their active state to switch the chip on; assume here the chip is enabled so we can focus on the outputs.) For address $A_{2} A_{1} A_{0} = 100$ , write out all eight output values $D_{0} \dots D_{7}$ .

Recall Solutions — Level 2

L2-Q1. $5$ in binary is $10 1_{2}$ , i.e. $A_{2} = 1, A_{1} = 0, A_{0} = 1$ . The picture below shows the rule that turns those bit values into the expression: a bit that is $1$ enters the AND in true form; a bit that is $0$ enters complemented (barred). Read the three cells left to right.

A minterm ANDs all inputs, using true form where the bit is $1$ and complement form where the bit is $0$ : $D_{5} = A_{2} \overline{A_{1}} A_{0} .$ Sanity: this equals $1$ only when $A_{2} A_{1} A_{0} = 101$ , which is exactly $5$ . ✓

L2-Q2. $D_{3} = E \cdot A_{1} \cdot A_{0}$ .

With $E = 0$ : $D_{3} = 0 \cdot 1 \cdot 1 = 0$ . In fact every output is $0$ — the chip is asleep. See figure s04: the enable pin acts as a master switch AND-ed into every output, so when it's $0$ the whole output bus goes low regardless of the address.
With $E = 1$ : $D_{3} = 1 \cdot 1 \cdot 1 = 1$ , and it's the only hot line (address $1 1_{2} = 3$ ).

L2-Q3. Address $10 0_{2} = 4$ , so line $4$ is "selected". Active-low means selected $= 0$ , unselected $= 1$ . The schematic below shows why the pattern is a single $0$ in a field of $1$ s: each active-low output has an inverting bubble, so the one minterm that is internally $1$ comes out as $0$ , while the seven internal $0$ s come out as $1$ . (A real 74138 reaches this "enabled" state only when all three of its enable pins are held in their active states; we assume that here.)

$D_{0} = 1, D_{1} = 1, D_{2} = 1, D_{3} = 1, D_{4} = 0, D_{5} = 1, D_{6} = 1, D_{7} = 1.$ The single zero marks the chosen output.

Level 3 — Analysis

Goal: reason about a function across all its input rows.

L3-Q1. A 3:8 decoder drives an OR gate. The OR is fed by outputs $D_{0}$ , $D_{3}$ , and $D_{6}$ . Write the function $F (A_{2}, A_{1}, A_{0})$ this circuit computes, as a sum of minterms and as a decimal set.

L3-Q2. For that same $F$ , fill in the truth-table column: for each of the 8 input rows, is $F = 0$ or $1$ ? State how many rows give $F = 1$ and why.

L3-Q3. A 2:4 decoder with active-high enable is used as a router. Data bit $x$ is wired to the enable pin; the address selects the destination. If $x = 1$ and address $= 10$ , what does each output read? If $x = 0$ and address $= 10$ ?

Recall Solutions — Level 3

L3-Q1. OR-ing decoder lines is literally OR-ing minterms (this is SOP). Recall the $\sum m$ shorthand defined at the top: it just names which lines to feed the OR. $F = D_{0} + D_{3} + D_{6} = \overline{A_{2}} \overline{A_{1}} \overline{A_{0}} + \overline{A_{2}} A_{1} A_{0} + A_{2} A_{1} \overline{A_{0}} .$ As a decimal set: $F = \sum m (0, 3, 6)$ .

L3-Q2. $F = 1$ on exactly the rows ${0, 3, 6}$ and $0$ everywhere else:

dec	$A_{2} A_{1} A_{0}$	$F$
0	000	1
1	001	0
2	010	0
3	011	1
4	100	0
5	101	0
6	110	1
7	111	0

Three rows give $1$ — one per minterm ORed in, because each decoder line is hot for exactly one address, and those addresses ( $0, 3, 6$ ) are distinct.

L3-Q3. With enable-as-data (a demultiplexer): each output is $D_{k} = x \cdot m_{k}$ . Address $1 0_{2} = 2$ selects line $2$ .

$x = 1$ : $D_{2} = 1$ , the rest $0$ . The data "1" is delivered to output 2.
$x = 0$ : $D_{2} = 0 \cdot 1 = 0$ , and every other output is $0$ too — the data "0" is delivered to output 2 (all lines read 0, but the selected one is faithfully carrying $x = 0$ ). Either way, output 2 mirrors $x$ and the others stay silent. That is routing.

Level 4 — Synthesis

Goal: build/design circuits, not just read them.

L4-Q1. Implement $F (A, B, C) = \sum m (2, 5, 7)$ using one 3:8 decoder plus a single OR gate. Give the wiring (which variable to which input) and the OR-gate connections.

L4-Q2. Build a 3:8 decoder from two 2:4 decoders that each have an active-high enable. Specify: what feeds the address inputs of each, and what drives each enable, so that the top handles lines $0$ – $3$ and the bottom handles $4$ – $7$ . Prove no two decoders can be on simultaneously.

L4-Q3. You only have decoders with active-low outputs (selected line $= 0$ ). You still want the SOP function $F = \sum m (1, 4)$ . What single gate do you place after the two selected lines to recover $F = 1$ on inputs 1 and 4? (Hint: think about what NAND does to two active-low signals.)

Recall Solutions — Level 4

L4-Q1. Wire the most significant function variable to the most significant decoder input: $A \to A_{2}$ , $B \to A_{1}$ , $C \to A_{0}$ . The decoder now outputs all eight minterms. OR together exactly the ones in the set. The figure shows the decoder box with only the three listed lines ( $D_{2}, D_{5}, D_{7}$ ) tapped into one OR gate — the physical meaning of $\sum m (2, 5, 7)$ :

$F = D_{2} + D_{5} + D_{7} .$ Check the minterms: $D_{2} = \overline{A} B \overline{C}$ (since $2 = 010$ ), $D_{5} = A \overline{B} C$ ( $5 = 101$ ), $D_{7} = A B C$ ( $7 = 111$ ). The 3-input OR gives $F$ . ✓

L4-Q2. (The hierarchical decoder trick from the parent note.) The figure below carries the whole argument — read it alongside these three wiring rules, and use the callout box in it to see the mutual-exclusion proof at a glance:

Feed $A_{1} A_{0}$ (the two low bits) to the address inputs of both 2:4 decoders (mint arrows).
Top decoder: enable $E_{top} = \overline{A_{2}}$ (through the NOT gate). Its outputs become $D_{0}, D_{1}, D_{2}, D_{3}$ .
Bottom decoder: enable $E_{bot} = A_{2}$ (direct). Its outputs become $D_{4}, D_{5}, D_{6}, D_{7}$ .

Proof of mutual exclusion (the white box in the figure): $E_{top} = \overline{A_{2}}$ and $E_{bot} = A_{2}$ . Their AND is $\overline{A_{2}} \cdot A_{2} = 0$ for every value of $A_{2}$ (a bit and its complement are never both $1$ ). So the two enables are never $1$ together — exactly one decoder is awake, and it fires exactly one of its four lines. One-hot over all eight is preserved. ∎

L4-Q3. With active-low outputs, the selected line reads $0$ . For input $1$ , line $D_{1} = 0$ ; for input $4$ , line $D_{4} = 0$ ; otherwise both are $1$ . A NAND gate outputs $1$ whenever any input is $0$ : $F = \overline{D_{1} \cdot D_{4}} .$

Input 1: $D_{1} = 0 \Rightarrow \overline{0 \cdot 1} = \overline{0} = 1$ . ✓
Input 4: $D_{4} = 0 \Rightarrow \overline{1 \cdot 0} = 1$ . ✓
Any other input: both are $1 \Rightarrow \overline{1 \cdot 1} = 0$ . ✓ Why NAND is exactly right here (the De Morgan reason). Let the active-high meaning of each line be $d_{1}$ = "input is 1" and $d_{4}$ = "input is 4". Active-low wiring means the physical wire carries the complement: $D_{1} = \overline{d_{1}}$ and $D_{4} = \overline{d_{4}}$ . We want $F = d_{1} + d_{4}$ (fire on input 1 OR input 4). Now apply De Morgan's law ( $\overline{P} \cdot \overline{Q} = \overline{P + Q}$ , read backwards): $F = d_{1} + d_{4} = \overline{\overline{d_{1}} \cdot \overline{d_{4}}} = \overline{D_{1} \cdot D_{4}},$ which is exactly a NAND of the two physical (active-low) wires. So NAND-of-active-low is OR-of-active-high — that is why one NAND replaces the OR when your outputs are active-low.

Level 5 — Mastery

Goal: prove, generalise, and handle degenerate cases.

Recall from the top of the page: $n$ is the number of address inputs, and an $n : 2^{n}$ decoder therefore has $2^{n}$ one-hot outputs. Keep that meaning of $n$ in mind for all three problems below.

L5-Q1. Prove that for an enabled $n : 2^{n}$ decoder (i.e. a decoder with $n$ address inputs), the OR of all $2^{n}$ outputs equals $1$ for every input. What does this tell you about the outputs as a set?

L5-Q2. How many 2:4 decoders (each with one active-high enable) do you need to build a 4:16 decoder, and what drives the enables? Generalise: to build an $(n + 1)$ -input decoder from $n$ -input decoders, how many do you need and what selects among them?

L5-Q3. Degenerate case. Consider a " $0$ -input decoder", $n = 0$ , so $2^{n} = 1$ (one output, zero address bits). What does it do? Then consider a $1$ -input decoder ( $n = 1$ , a $1 : 2$ decoder). Write its two output equations and say what familiar gate each output is.

Recall Solutions — Level 5

L5-Q1. Each output is the minterm $m_{k}$ . The sum (OR) of all minterms of $n$ variables is the constant $1$ — this is a standard identity: every possible input row is covered by exactly one minterm, so for any input, precisely one $m_{k} = 1$ and the OR is $1$ . Formally, $\sum_{k = 0}^{2^{n} - 1} m_{k} = 1$ . What it tells us: the outputs are exhaustive and mutually exclusive — they partition all input space. Exactly one is hot at all times (when enabled). This is the mathematical statement of "one-hot".

L5-Q2. A 4:16 has $2^{4} = 16$ outputs; a 2:4 supplies $4$ outputs, so you need $16/4 = 4$ lower decoders for the outputs, plus one extra 2:4 acting as the selector that decodes the two high address bits $A_{3} A_{2}$ into four enable signals. So 5 decoders total (4 workers + 1 chooser).

Low bits $A_{1} A_{0}$ go to all four worker decoders.
Selector decodes $A_{3} A_{2}$ ; its four one-hot outputs become the four enables — exactly one worker awake at a time.

Generalisation: to go from $n$ -input to $(n + 1)$ -input you double the outputs, so you need two $n$ -input decoders, with the single new top bit $A_{n}$ selecting between them: enable one with $A_{n}$ , the other with $\overline{A_{n}}$ . (This is the recursive doubling behind memory address decoding.)

L5-Q3.

$n = 0$ : no address bits, $2^{0} = 1$ output. Nothing to choose — the single output is always the selected one. With an enable it becomes $D_{0} = E$ : it just passes the enable through. A decoder with zero address bits is a plain wire/enable.
$1 : 2$ decoder ( $n = 1$ ), one input $A_{0}$ , two outputs: $D_{0} = \overline{A_{0}}, D_{1} = A_{0} .$ $D_{0}$ is an inverter (NOT gate) of $A_{0}$ ; $D_{1}$ is just $A_{0}$ itself (a wire/buffer). So the smallest real decoder is "a bit and its complement" — the atom every larger decoder is built from.

Connections

Minterms and Maxterms — every exercise here rests on "output = minterm".
Sum of Products (SOP) — L3/L4 turn decoders into any SOP with one gate.
Demultiplexers — L3-Q3 and the enable-as-data idea.
Multiplexers — the complementary block; contrast with routing.
Encoders — the inverse; useful sanity check on direction.
Memory Address Decoding — L5 expansion is exactly how RAM rows/chips are selected.
7-Segment Display Driver — a downstream user of decoded outputs.

Exercises — Decoders (2 - 4, 3 - 8)