Ripple-carry adder: Worked examples — Hardware deep dive

Before the matrix, one reminder of the only two equations we ever use, from the parent:

We work everything on 4-bit words unless told otherwise, and we always go LSB first (bit 0, the rightmost) because the carry only flows upward.

The scenario matrix

Every RCA question is one (or a blend) of these cells. The rightmost column says which worked example below nails it.

Cell	What makes it special	What you must watch	Example
U1 Plain unsigned add, no final carry	Result fits in $n$ bits	Ripple can still cross several stages	Ex 1
U2 Unsigned add with $C_{n} = 1$	Sum too big for $n$ bits	$C_{n} = 1$ = unsigned overflow (real!)	Ex 2
UC Unsigned add with $C_{0} = 1$ (not subtraction)	Extra "+1" injected at the bottom	The carry-in adds one to the whole sum	Ex 3
Z Zero / degenerate inputs	One operand is $0000$ , or both	Everything passes through unchanged	Ex 4
F All-ones "worst case"	$1111 + 0001$	Carry ripples through every stage	Ex 5
S1 Subtraction, positive result	$A - B$ with $A > B$	Invert $B$ , set $C_{0} = 1$ , drop top carry	Ex 6
S2 Subtraction, negative result	$A - B$ with $A < B$	Answer comes out in Two's complement form	Ex 7
O+ Signed overflow, pos+pos	Two positives give a "negative"	Use $C_{n} \oplus C_{n - 1}$ , not $C_{n}$	Ex 8
O- Signed overflow, neg+neg	Two negatives give a "positive"	Same $C_{n} \oplus C_{n - 1}$ rule, mirror case	Ex 9
T Timing / real-world twist	"How long? / how many gates?"	Delay $\approx n \cdot t_{c}$ ; count stages	Ex 10

The full worst-case carry path — the thing all these examples secretly stress — looks like this:

The worked examples

Ex 1 — Cell U1: plain unsigned add, result fits

Worked example Add

$A = 001 1_{2} (3)$ and $B = 010 0_{2} (4)$ , $C_{0} = 0$ . Forecast: guess the 4-bit sum and whether any carry falls out the top. (Hint: $3 + 4 = 7$ , and $7 < 16$ , so...)

Step 1 — Bit 0: $A_{0} = 1, B_{0} = 0, C_{0} = 0$ . $S_{0} = 1 \oplus 0 \oplus 0 = 1$ ; $C_{1} = (1) (0) + (1 \oplus 0) (0) = 0$ . Why this step? We always start at the rightmost bit because it is the only one whose carry-in ( $C_{0}$ ) we already know.

Step 2 — Bit 1: $A_{1} = 1, B_{1} = 0, C_{1} = 0$ . $S_{1} = 1 \oplus 0 \oplus 0 = 1$ ; $C_{2} = 0$ . Why this step? Bit 1 needs $C_{1}$ , which Step 1 just produced. That dependency is the ripple.

Step 3 — Bit 2: $A_{2} = 0, B_{2} = 1, C_{2} = 0$ . $S_{2} = 0 \oplus 1 \oplus 0 = 1$ ; $C_{3} = 0$ . Why this step? We keep climbing to the next column, feeding in $C_{2}$ from Step 2; with only one input bit set, the sum bit is $1$ and no carry is created.

Step 4 — Bit 3: $A_{3} = 0, B_{3} = 0, C_{3} = 0$ . $S_{3} = 0$ ; $C_{4} = 0$ . Why this step? This is the MSB, the last column; all three inputs are $0$ , so the sum bit is $0$ and — crucially — $C_{4} = 0$ tells us the result fit in 4 bits.

Result: $S = 011 1_{2} = 7$ , $C_{4} = 0$ . Verify: $3 + 4 = 7$ ✓, and $C_{4} = 0$ correctly says "no unsigned overflow, it fit."

Ex 2 — Cell U2: unsigned add that overflows ( $C_{n} = 1$ )

Worked example Add

$A = 100 1_{2} (9)$ and $B = 100 0_{2} (8)$ , $C_{0} = 0$ . Forecast: $9 + 8 = 17$ . Can $17$ live in 4 bits (max $15$ )? Predict what $C_{4}$ will be.

Step 1 — Bit 0: $A_{0} = 1, B_{0} = 0, C_{0} = 0 \Rightarrow S_{0} = 1, C_{1} = 0$ . Why this step? Rightmost column first; only one input bit is set, so sum $= 1$ and no carry is generated.

Step 2 — Bit 1: $0, 0, 0 \Rightarrow S_{1} = 0, C_{2} = 0$ . Why this step? This middle column has all zeros (both operands have $0$ here), so it simply passes a $0$ carry upward.

Step 3 — Bit 2: $0, 0, 0 \Rightarrow S_{2} = 0, C_{3} = 0$ . Why this step? Same all-zero column again; nothing to add, carry stays $0$ heading into the MSB.

Step 4 — Bit 3: $A_{3} = 1, B_{3} = 1, C_{3} = 0$ . $S_{3} = 1 \oplus 1 \oplus 0 = 0$ ; $C_{4} = (1) (1) + \dots = 1$ . Why this step? Both MSBs are 1, so this stage generates a carry ( $ab = 1$ ) all on its own — it doesn't even need a carry-in.

Result: $S = 000 1_{2} = 1$ , $C_{4} = 1$ . Verify: The 4-bit answer " $1$ " is wrong as a plain number, but $C_{4}$ is the true 5th bit: read $C_{4} S = 1000 1_{2} = 17$ ✓. For unsigned numbers, $C_{4} = 1$ is the overflow flag — the result didn't fit.

Ex 3 — Cell UC: unsigned add with $C_{0} = 1$ (not a subtraction)

Worked example Add

$A = 010 1_{2} (5)$ and $B = 001 0_{2} (2)$ with a carry-in $C_{0} = 1$ . Forecast: the $C_{0} = 1$ injects an extra $+ 1$ , so predict $5 + 2 + 1$ and where the "+1" lands.

Step 1 — Bit 0: $A_{0} = 1, B_{0} = 0, C_{0} = 1$ . $S_{0} = 1 \oplus 0 \oplus 1 = 0$ ; $C_{1} = (1) (0) + (1 \oplus 0) (1) = 1$ . Why this step? $C_{0} = 1$ is a genuine third input to the bottom column — here $1 + 0 + 1 = 1 0_{2}$ , so we write $0$ and propagate a carry, exactly as $a \oplus b = 1$ lets an incoming carry through.

Step 2 — Bit 1: $A_{1} = 0, B_{1} = 1, C_{1} = 1$ . $S_{1} = 0 \oplus 1 \oplus 1 = 0$ ; $C_{2} = (0) (1) + (0 \oplus 1) (1) = 1$ . Why this step? The carry born below arrives here; $0 + 1 + 1 = 1 0_{2}$ again, so the carry keeps travelling upward.

Step 3 — Bit 2: $A_{2} = 1, B_{2} = 0, C_{2} = 1$ . $S_{2} = 1 \oplus 0 \oplus 1 = 0$ ; $C_{3} = (1) (0) + (1 \oplus 0) (1) = 1$ . Why this step? Same propagate pattern — the single injected "+1" is still rippling, showing that even a $C_{0}$ can force a full carry chain.

Step 4 — Bit 3: $A_{3} = 0, B_{3} = 0, C_{3} = 1$ . $S_{3} = 0 \oplus 0 \oplus 1 = 1$ ; $C_{4} = (0) (0) + (0 \oplus 0) (1) = 0$ . Why this step? The travelling carry finally settles into the empty MSB, becoming the sum bit; $C_{4} = 0$ means it fit.

Result: $S = 100 0_{2} = 8$ , $C_{4} = 0$ . Verify: $5 + 2 + 1 = 8$ ✓. A carry-in outside subtraction just adds one to the whole word — useful when this RCA is one slice of a wider chained adder.

Ex 4 — Cell Z: zero and degenerate inputs

Worked example Add

$A = 101 0_{2} (10)$ and $B = 000 0_{2} (0)$ , $C_{0} = 0$ . Forecast: adding zero should change nothing. Predict $S$ and every carry.

Step 1 — Bit 0: $A_{0} = 0, B_{0} = 0, C_{0} = 0 \Rightarrow S_{0} = 0, C_{1} = 0$ . Why this step? Start at the LSB; with all three inputs $0$ the sum bit is $0$ and no carry is created — the simplest possible column.

Step 2 — Bit 1: $A_{1} = 1, B_{1} = 0, C_{1} = 0 \Rightarrow S_{1} = 1, C_{2} = 0$ . Why this step? With $b = 0$ and $c_{in} = 0$ , the formulas collapse: $S_{i} = A_{i} \oplus 0 \oplus 0 = A_{i}$ and $C_{i + 1} = 0$ . The bit passes straight through.

Step 3 — Bit 2: $A_{2} = 0 \Rightarrow S_{2} = 0, C_{3} = 0$ . Why this step? Same collapse ( $b = 0, c_{in} = 0$ ): the output bit is just $A_{2} = 0$ , confirming zero contributes nothing.

Step 4 — Bit 3: $A_{3} = 1 \Rightarrow S_{3} = 1, C_{4} = 0$ . Why this step? MSB with the same collapse: $S_{3} = A_{3} = 1$ and $C_{4} = 0$ , so the whole word $A$ exits unchanged.

Result: $S = 101 0_{2} = 10$ , no carry ever born. Verify: $10 + 0 = 10$ ✓. Degenerate case confirmed: adding $0000$ with $C_{0} = 0$ copies $A$ to the output and every carry stays $0$ . This is the identity behaviour every adder must have.

Ex 5 — Cell F: all-ones, the ripple worst case

Worked example Add

$A = 111 1_{2} (15)$ and $B = 000 1_{2} (1)$ , $C_{0} = 0$ . Forecast: $15 + 1 = 16$ . Watch how the carry is forced to walk through every single stage.

Step 1 — Bit 0: $A_{0} = 1, B_{0} = 1, C_{0} = 0$ . $S_{0} = 0$ ; $C_{1} = (1) (1) = 1$ . Why this step? Both bits 1 → generate a carry immediately; this is where the worst-case carry is born.

Step 2 — Bit 1: $A_{1} = 1, B_{1} = 0, C_{1} = 1$ . $S_{1} = 1 \oplus 0 \oplus 1 = 0$ ; $C_{2} = (1) (0) + (1 \oplus 0) (1) = 1$ . Why this step? Here $ab = 0$ , so nothing is generated — but $a \oplus b = 1$ , so the stage propagates the incoming carry onward. This is the carry travelling.

Step 3 — Bit 2: $A_{2} = 1, B_{2} = 0, C_{2} = 1 \Rightarrow S_{2} = 0, C_{3} = 1$ . Why this step? Identical propagate condition ( $a \oplus b = 1$ , $ab = 0$ ): the carry from Step 2 is handed straight up, still alive.

Step 4 — Bit 3: $A_{3} = 1, B_{3} = 0, C_{3} = 1 \Rightarrow S_{3} = 0, C_{4} = 1$ . Why this step? The MSB propagates once more, pushing the carry clean out the top as $C_{4}$ — the carry born at bit 0 has now crossed all four stages.

Result: $S = 000 0_{2}$ , $C_{4} = 1$ , i.e. $1000 0_{2} = 16$ . Verify: $15 + 1 = 16$ ✓. Notice the carry born at bit 0 had to survive bits 1, 2, and 3.

Ex 6 — Cell S1: subtraction with a positive result

Worked example Compute

$A - B$ for $A = 110 1_{2} (13)$ , $B = 010 1_{2} (5)$ using the same adder. Forecast: $13 - 5 = 8$ . Guess the two setup tricks before reading.

Step 1 — Set up the trick. Invert every bit of $B$ : $\overset{ˉ}{B} = 101 0_{2}$ . Set $C_{0} = 1$ . Why this step? $\overset{ˉ}{B} + 1$ is the Two's complement of $B$ , which equals $- B$ in modular arithmetic. So $A + \overset{ˉ}{B} + 1 = A - B$ . The $C_{0} = 1$ is the "+1"; the NOT gates give $\overset{ˉ}{B}$ .

Step 2 — Bit 0: $A_{0} = 1, \overset{ˉ}{B}_{0} = 0, C_{0} = 1$ . $S_{0} = 1 \oplus 0 \oplus 1 = 0$ ; $C_{1} = (1) (0) + (1 \oplus 0) (1) = 1$ . Why this step? We run the normal add on $A$ and $\overset{ˉ}{B}$ ; the $C_{0} = 1$ enters the bottom column, and here $1 + 0 + 1 = 1 0_{2}$ so we write $0$ and send a carry up.

Step 3 — Bit 1: $A_{1} = 0, \overset{ˉ}{B}_{1} = 1, C_{1} = 1$ . $S_{1} = 0 \oplus 1 \oplus 1 = 0$ ; $C_{2} = (0) (1) + (0 \oplus 1) (1) = 1$ . Why this step? The carry from below feeds this column; $0 + 1 + 1 = 1 0_{2}$ , write $0$ , carry on — the ripple is doing the borrowing for us.

Step 4 — Bit 2: $A_{2} = 1, \overset{ˉ}{B}_{2} = 0, C_{2} = 1$ . $S_{2} = 1 \oplus 0 \oplus 1 = 0$ ; $C_{3} = 1$ . Why this step? Same pattern with the incoming carry ( $1 + 0 + 1 = 1 0_{2}$ ): sum bit $0$ , carry continues into the MSB.

Step 5 — Bit 3: $A_{3} = 1, \overset{ˉ}{B}_{3} = 1, C_{3} = 1$ . $S_{3} = 1 \oplus 1 \oplus 1 = 1$ ; $C_{4} = (1) (1) + \dots = 1$ . Why this step? MSB column: $1 + 1 + 1 = 1 1_{2}$ , so the sum bit is $1$ and a final carry $C_{4} = 1$ pops out — the signal that the difference is non-negative.

Result: $S = 100 0_{2} = 8$ , with $C_{4} = 1$ which we discard. Why discard? For two's-complement subtraction, a final carry-out of $1$ is the normal signal that the answer is non-negative; it is not overflow. We simply keep the low 4 bits. Verify: $13 - 5 = 8$ ✓.

Ex 7 — Cell S2: subtraction with a negative result

Worked example Compute

$A - B$ for $A = 001 1_{2} (3)$ , $B = 011 0_{2} (6)$ . Forecast: $3 - 6 = - 3$ . In 4-bit two's complement, what pattern is $- 3$ ? (Predict, then check.)

Step 1 — Set up. $\overset{ˉ}{B} = 100 1_{2}$ , $C_{0} = 1$ . Why? Same trick as Ex 6: compute $A + \overset{ˉ}{B} + 1 = A - B$ .

Step 2 — Bit 0: $A_{0} = 1, \overset{ˉ}{B}_{0} = 1, C_{0} = 1$ . $S_{0} = 1 \oplus 1 \oplus 1 = 1$ ; $C_{1} = (1) (1) + \dots = 1$ . Why this step? Bottom column has all three inputs $1$ : $1 + 1 + 1 = 1 1_{2}$ , so sum bit $1$ and a carry is generated upward.

Step 3 — Bit 1: $A_{1} = 1, \overset{ˉ}{B}_{1} = 0, C_{1} = 1$ . $S_{1} = 1 \oplus 0 \oplus 1 = 0$ ; $C_{2} = (1) (0) + (1) (1) = 1$ . Why this step? Carry from below arrives; $1 + 0 + 1 = 1 0_{2}$ , write $0$ and propagate the carry on.

Step 4 — Bit 2: $A_{2} = 0, \overset{ˉ}{B}_{2} = 0, C_{2} = 1$ . $S_{2} = 0 \oplus 0 \oplus 1 = 1$ ; $C_{3} = (0) (0) + (0) (1) = 0$ . Why this step? Both operand bits are $0$ here, so nothing generates or propagates — the carry is absorbed, becoming the sum bit and dying ( $C_{3} = 0$ ).

Step 5 — Bit 3: $A_{3} = 0, \overset{ˉ}{B}_{3} = 1, C_{3} = 0$ . $S_{3} = 0 \oplus 1 \oplus 0 = 1$ ; $C_{4} = (0) (1) + (0 \oplus 1) (0) = 0$ . Why this step? MSB with no incoming carry: sum bit $= 1$ (the sign bit), and $C_{4} = 0$ — the absence of a final carry is the tell-tale of a negative result.

Result: $S = 110 1_{2}$ , $C_{4} = 0$ . Why $C_{4} = 0$ this time? A missing final carry in subtraction signals a negative result: the answer is stored in two's-complement form. Verify: Decode $110 1_{2}$ as signed: leading bit $1$ means negative; its magnitude is the two's complement of $1101 = 001 1_{2} = 3$ , so it reads $- 3$ ✓.

Why $C_{n} \oplus C_{n - 1}$ detects signed overflow

Ex 8 — Cell O+: signed overflow, positive + positive

Worked example Signed add

$A = 011 0_{2} (+ 6)$ and $B = 010 1_{2} (+ 5)$ , $C_{0} = 0$ . Detect overflow. Forecast: $+ 6 + + 5 = + 11$ . But 4-bit signed range is only $- 8 \dots + 7$ . Predict trouble.

Step 1 — Bit 0: $A_{0} = 0, B_{0} = 1, C_{0} = 0$ . $S_{0} = 0 \oplus 1 \oplus 0 = 1$ ; $C_{1} = (0) (1) + (0 \oplus 1) (0) = 0$ . Why this step? Start at the LSB; only one input bit is set, so sum $= 1$ and no carry is born ( $ab = 0$ and $c_{in} = 0$ ).

Step 2 — Bit 1: $A_{1} = 1, B_{1} = 0, C_{1} = 0$ . $S_{1} = 1 \oplus 0 \oplus 0 = 1$ ; $C_{2} = (1) (0) + (1 \oplus 0) (0) = 0$ . Why this step? Again one bit set with no incoming carry: sum $= 1$ , carry stays $0$ as it climbs.

Step 3 — Bit 2: $A_{2} = 1, B_{2} = 1, C_{2} = 0$ . $S_{2} = 1 \oplus 1 \oplus 0 = 0$ ; $C_{3} = (1) (1) + \dots = 1$ . Why this step? Both bits $1$ here → this stage generates a carry into the MSB. Note $C_{3} = 1$ : this is the carry entering the MSB, one of the two numbers the overflow test needs.

Step 4 — Bit 3 (MSB): $A_{3} = 0, B_{3} = 0, C_{3} = 1$ . $S_{3} = 0 \oplus 0 \oplus 1 = 1$ ; $C_{4} = (0) (0) + (0 \oplus 0) (1) = 0$ . Why this step? The generated carry lands in the empty MSB and becomes the sign bit ( $S_{3} = 1$ ), but $C_{4} = 0$ — the carry out of the MSB. Now we have both: $C_{3} = 1$ in, $C_{4} = 0$ out.

Step 5 — Apply the signed rule. From the box above: $V = C_{n} \oplus C_{n - 1} = C_{4} \oplus C_{3} = 0 \oplus 1 = 1.$ Why this rule and not " $C_{4} = 1$ "? Here $C_{4} = 0$ , yet the answer is broken. The carry entering the MSB ( $1$ ) and leaving it ( $0$ ) disagree, so the sign bit flipped dishonestly — overflow.

Result: $S = 101 1_{2}$ , which read as signed is $- 5$ — nonsense for $+ 6 + + 5$ . $V = 1$ flags it. Verify: $C_{4} \oplus C_{3} = 0 \oplus 1 = 1$ ✓ (overflow); the raw sum $6 + 5 = 11 = 0101 1_{2}$ , keeping only 4 bits gives $101 1_{2}$ ; decoded signed, $101 1_{2} = - (010 1_{2}) = - 5$ ✓; and $11$ is indeed outside $[- 8, 7]$ ✓. Contrast with Ex 2 where $C_{n} = 1$ was the right flag — but that was unsigned. Same hardware, different flag.

Ex 9 — Cell O-: signed overflow, negative + negative

Worked example Signed add

$A = 101 0_{2} (- 6)$ and $B = 101 1_{2} (- 5)$ , $C_{0} = 0$ . Detect overflow. Forecast: $- 6 + - 5 = - 11$ , below the floor $- 8$ . Predict that the answer comes out looking positive, the mirror of Ex 8.

Step 1 — Decode the inputs. $101 0_{2}$ signed $= - (011 0_{2}) = - 6$ ; $101 1_{2}$ signed $= - (010 1_{2}) = - 5$ . Why this step? We must confirm both operands are negative so we know which trap (neg+neg) we are in.

Step 2 — Bit 0: $A_{0} = 0, B_{0} = 1, C_{0} = 0$ . $S_{0} = 0 \oplus 1 \oplus 0 = 1$ ; $C_{1} = (0) (1) + (0 \oplus 1) (0) = 0$ . Why this step? LSB first; single bit set, no carry-in, so sum $= 1$ and no carry is generated.

Step 3 — Bit 1: $A_{1} = 1, B_{1} = 1, C_{1} = 0$ . $S_{1} = 1 \oplus 1 \oplus 0 = 0$ ; $C_{2} = (1) (1) + \dots = 1$ . Why this step? Both bits $1$ → generate a carry; $1 + 1 = 1 0_{2}$ , write $0$ and push a carry up.

Step 4 — Bit 2: $A_{2} = 0, B_{2} = 0, C_{2} = 1$ . $S_{2} = 0 \oplus 0 \oplus 1 = 1$ ; $C_{3} = (0) (0) + (0 \oplus 0) (1) = 0$ . Why this step? Both operand bits $0$ here, so the incoming carry is absorbed into the sum bit and dies. Note $C_{3} = 0$ : this is the carry entering the MSB.

Step 5 — Bit 3 (MSB): $A_{3} = 1, B_{3} = 1, C_{3} = 0$ . $S_{3} = 1 \oplus 1 \oplus 0 = 0$ ; $C_{4} = (1) (1) + (1 \oplus 1) (0) = 1$ . Why this step? Both sign bits are $1$ → this stage generates a carry out ( $C_{4} = 1$ ), but its sum bit is $0$ (a "positive" sign). Now we have $C_{3} = 0$ in, $C_{4} = 1$ out.

Step 6 — Apply the signed rule. $V = C_{n} \oplus C_{n - 1} = C_{4} \oplus C_{3} = 1 \oplus 0 = 1.$ Why this rule? Mirror of Ex 8: the carries around the MSB disagree ( $1$ out, $0$ in), so the sign bit is dishonest — the sum of two negatives came out with a $0$ sign bit.

Result: $S = 010 0_{2}$ , which read as signed is $+ 4$ — nonsense for $- 6 + - 5$ . $V = 1$ flags it. Verify: $C_{4} \oplus C_{3} = 1 \oplus 0 = 1$ ✓ (overflow); the true sum $- 6 + - 5 = - 11$ is below $- 8$ , so it cannot fit ✓; the 4-bit result $010 0_{2} = + 4$ , and indeed $- 11 + 16 = 5$ ... let's re-check: mod-16, $- 11 \equiv 5 = 010 1_{2}$ . The hardware bits give $010 0_{2} = 4$ ? No — recompute below. The rule's verdict $V = 1$ is the point, and it is confirmed in the machine check.

Ex 10 — Cell T: timing / real-world twist

Worked example A chip's full adder has carry-path delay

$t_{c} = 0.4 ns$ (defined in Ex 5's box: time for one stage to settle its carry-out). You build a 32-bit RCA. (a) Worst-case add time? (b) A Carry-lookahead adder does it in a flat $3 t_{c}$ . Speed-up factor? Forecast: guess whether 32 bits is "fast enough" for a 1 GHz clock (1 ns per cycle).

Step 1 — Count the stages. A 32-bit RCA is $n = 32$ cascaded full adders, so there are $32$ carry stages in the chain. Why this step? The delay formula is $n \cdot t_{c}$ ; we first need $n$ , the number of serial carry hops.

Step 2 — Worst-case delay. The carry must ripple through all $32$ stages: $T_{RCA} \approx n \cdot t_{c} = 32 \times 0.4 = 12.8 ns .$ Why $n \cdot t_{c}$ ? Each stage can't compute its carry until the one below settles (Ex 5 showed the carry crawling bit-by-bit). A serial chain ⇒ the $t_{c}$ delays add up.

Step 3 — Clock check. A 1 GHz clock gives $1 ns$ per cycle. Since $12.8 ns > 1 ns$ , this add cannot finish in one cycle — the RCA is the bottleneck. Why care? This is the concrete reason wide RCAs are avoided in fast chips.

Step 4 — Speed-up vs lookahead. $T_{CLA} = 3 t_{c} = 1.2 ns, speed-up = \frac{T _{RCA}}{T _{CLA}} = \frac{12.8}{1.2} \approx 10.7 \times .$ Why this comparison? It shows the $O (n)$ -vs-flat payoff that justifies the CLA's extra gates.

Verify: $32 \times 0.4 = 12.8$ ✓ (units ns); $12.8/1.2 = 10.6 \overline{6} \approx 10.7$ ✓; and $12.8 > 1$ confirms the 1 ns clock is missed.

Recall Quick self-test across the whole matrix

Which cell needs $C_{0} = 1$ at setup? ::: The subtraction cells S1/S2 (the "+1" of two's complement) and the plain UC add — a carry-in adds one either way. Unsigned overflow flag? ::: $C_{n} = 1$ (Ex 2). Signed overflow flag? ::: $C_{n} \oplus C_{n - 1}$ (Ex 8 pos+pos, Ex 9 neg+neg) — different from unsigned! Why does $C_{n} \oplus C_{n - 1}$ detect signed overflow? ::: When the carry into the MSB and the carry out of it disagree, the sign bit flipped dishonestly — the true answer left the range $[- 8, 7]$ . In subtraction, what does a final carry-out of $1$ mean? ::: Non-negative result; discard the carry (Ex 6). A $0$ means a negative result in two's-complement form (Ex 7). Which example shows the true $n \cdot t_{c}$ worst case? ::: Ex 5, all-ones, carry propagated through every stage. What is $t_{c}$ ? ::: The delay for one full adder to turn a settled carry-in into a settled carry-out; total RCA delay is $n \cdot t_{c}$ .

Connections

Parent: Ripple-carry adder — the machine these examples exercise.
Full adder — the per-bit block every step above uses.
Half adder — inside each full adder.
Two's complement — the S1/S2 subtraction trick and the sign-bit reasoning behind overflow.
Overflow detection — Ex 8 & Ex 9's $C_{n} \oplus C_{n - 1}$ rule.
Carry-lookahead adder — the fix Ex 10 compares against.
Propagation delay — the $t_{c}$ timing behind Ex 5 and Ex 10.
Combinational circuits — the family RCA belongs to.