Ripple-carry adder: Question bank — Hardware deep dive

Definition Boolean notation used on this page (read this first)

Digital-logic writing borrows the look of ordinary algebra but the operators mean logic gates, not arithmetic. Before any symbol appears in a trap, here is exactly what each one does — anchored to the picture below.

$\oplus$ is XOR ("exclusive or"): outputs $1$ when its two inputs differ, $0$ when they match. It answers "are these two bits different?"
Juxtaposition like $ab$ (two symbols touching) means AND: outputs $1$ only when both are $1$ . Think "and gate" = "all must agree on 1."
The plus sign $+$ means OR, not arithmetic addition: outputs $1$ when at least one input is $1$ . So $ab + b c_{in} + a c_{in}$ reads "this OR that OR that."
A bar like $\overset{ˉ}{B}$ means NOT (invert every bit): each $0$ becomes $1$ and each $1$ becomes $0$ .

The one place where $+$ does mean arithmetic is inside a decimal statement like " $5 + 3 = 8$ " or "the sum $\geq 2$ " — context makes it clear. Inside a Boolean expression, $+$ is always OR.

Every symbol used here comes straight from the parent note: $a, b, c_{in}$ are the three single bits going into one Full adder; $s$ is its sum bit; $c_{o u t}$ is its carry-out bit; $A_{i}, B_{i}$ are bit $i$ of the two numbers; $C_{i}$ is the carry entering stage $i$ ; $C_{n}$ is the final carry-out; $t_{c}$ is the time for a carry to cross one stage; $n$ is the word width in bits.

True or false — justify

True or false: the sum output

s

and the carry output

c_{o u t}

can each be built from XOR gates alone.

False —

s

is XOR (odd parity), but

c_{o u t}

is the majority function

ab + b c_{in} + a c_{in}

(AND-of-pairs OR'd together), which XOR cannot express because XOR flips at every extra 1 while majority only cares about crossing "at least two."

True or false: all

n

full adders in a ripple-carry adder finish computing at the same instant.

False — the inputs

A_{i}, B_{i}

arrive together, but each stage's correct

C_{i + 1}

waits for

C_{i}

, so the top stage settles only after the carry ripples through, roughly

n \cdot t_{c}

(see the ripple figure and the timing waveform).

True or false: a carry-out of

1

from the whole adder always means the answer is wrong.

False — for unsigned numbers

C_{n} = 1

means the true sum did not fit, but for signed Two's complement numbers

C_{n}

can be

1

on a perfectly correct result; signed overflow is

C_{n} \oplus C_{n - 1}

True or false: the ripple-carry adder is a combinational circuit even though the carry "travels" through it.

True — "travels" describes propagation delay, not memory; the output is still purely a function of the current inputs, so it is a combinational circuit with no stored state.

True or false: swapping the two inputs

a

and

b

of a full adder changes its outputs.

False — both

s = a \oplus b \oplus c_{in}

and

c_{o u t} = ab + b c_{in} + a c_{in}

are symmetric in

a

and

b

, so the full adder treats them interchangeably.

True or false: doubling the word width

n

roughly doubles both the delay and the gate count of a ripple-carry adder.

True — delay is

\approx n \cdot t_{c}

(linear) and area is one full adder per bit (linear), so both scale as

O (n)

; the Carry-lookahead adder breaks the delay scaling, not the area.

True or false: setting

C_{0} = 1

instead of

0

never affects the sum.

False —

C_{0}

is a genuine input to bit 0; setting it to

1

adds one to the total and is exactly the trick used with inverted

B

to perform subtraction via Two's complement.

True or false: "generate" and "propagate" are two different physical wires, so a stage can do both at once.

Partly — generate

ab

(AND) and propagate

a \oplus b

(XOR) are distinct nets, but they can't both make a carry from the same incoming bit: propagate needs a carry to pass, generate makes one regardless, and

c_{o u t} = ab + (a \oplus b) c_{in}

OR's the two paths together (see the half-adder decomposition figure).

Spot the error

Spot the error: "Since

s

uses XOR of all three bits,

c_{o u t} = a \oplus b \oplus c_{in}

by symmetry."

XOR measures odd count of 1s; carry measures magnitude reaching 2. They agree at some rows and disagree at others (e.g.

a = b = 1, c_{in} = 0

: XOR

= 0

but carry

= 1

), so

c_{o u t}

must be the majority OR-of-ANDs, not XOR.

Spot the error: "The MSB sum bit is ready as soon as the input bits arrive, since all inputs enter together."

The MSB sum depends on

C_{n - 1}

, which chains back to

C_{0}

; the carry path is serial, so the MSB only settles after

\approx n \cdot t_{c}

of Propagation delay — exactly the late-rising top trace in the timing figure.

Spot the error: "To subtract

A - B

, invert

B

and leave

C_{0} = 0

Inverting

B

(the

\overset{ˉ}{B}

NOT operation) gives the one's complement; you still need the

+ 1

, supplied by

C_{0} = 1

, so that

A + \overset{ˉ}{B} + 1 = A - B

. Leaving

C_{0} = 0

produces

A - B - 1

Spot the error: "For signed numbers, ignore

C_{n}

and just check the MSB of the result to detect overflow."

The result MSB is the sign bit, not the overflow flag; correct signed Overflow detection compares the carry into the MSB with the carry out of it:

C_{n} \oplus C_{n - 1}

Spot the error: "A carry-out

C_{4}

in a 4-bit subtraction means the subtraction overflowed."

In Two's complement subtraction the extra

C_{n}

is expected and simply discarded; a

C_{n} = 1

there signals a non-negative result, not overflow.

Spot the error: "Because RCA is

O (n)

delay, a 64-bit RCA is exactly twice as slow as a 32-bit one at any moment during the add."

The

O (n)

describes worst-case settling time, not a continuous ratio; the delay only matters once, when the longest carry chain is exercised, and constants and the LSB timing mean it's about double, not exactly.

Spot the error: "The half adder and full adder are the same thing since both add bits."

A Half adder adds only two bits and has no carry-in; a Full adder adds three (including

c_{in}

) and equals two half adders plus an OR gate on their two carry bits — exactly the wiring in the first figure.

Why questions

Why is the carry-out defined by "at least two 1s" rather than "the sum is large"?

Because three single bits sum to at most

3

, and "≥ 2" is exactly the condition that the twos-place bit

c_{o u t}

turns on; "at least two 1s" is the majority function that captures this.

Why can't we compute all the carries in parallel in a plain ripple-carry adder?

Each

C_{i + 1} = A_{i} B_{i} + (A_{i} \oplus B_{i}) C_{i}

literally contains

C_{i}

as an input, so the value isn't defined until the previous carry is known — a chained dependency the Carry-lookahead adder deliberately unrolls.

Why does the same hardware add and subtract with only a "subtract" control line?

A controlled XOR conditionally inverts each

B_{i}

, and the subtract line also drives

C_{0}

; setting both to 1 turns

A + B

into

A + \overset{ˉ}{B} + 1 = A - B

using Two's complement.

Why is

O (n)

gate count considered good while

O (n)

delay is considered bad?

Linear area means the circuit is small and cheap and regular; but linear delay means speed degrades directly with word width, which is unacceptable for wide fast processors — hence faster carry schemes.

Why does overflow use

C_{n} \oplus C_{n - 1}

instead of just

C_{n}

Signed overflow happens when adding two same-sign numbers flips the sign bit wrongly; that flip occurs exactly when the carry into the MSB differs from the carry out of it, which is what the XOR detects.

Why do we say the carry "ripples" rather than "jumps"?

The correct carry cannot skip stages — it must be resolved at each bit before the next can resolve, so it moves like a wave one stage at a time from LSB to MSB (the arrow chain in the ripple figure).

Edge cases

Edge case: what does a full adder output when

a = b = c_{in} = 0

s = 0

and

c_{o u t} = 0

— the trivial zero row; both parity and majority agree that nothing happens.

Edge case: what does a full adder output when

a = b = c_{in} = 1

Sum in decimal is

3 = 1 1_{2}

, so

s = 1

(odd count) and

c_{o u t} = 1

(majority holds); this is the row that most clearly separates XOR from majority.

Edge case: what happens if

C_{0} = 1

but you are doing ordinary addition, not subtraction?

You get

A + B + 1

;

C_{0}

is a real operand, so a stray

1

there silently adds one to your result — a common wiring bug.

Edge case: for a 1-bit "ripple-carry adder" (

n = 1

), is the ripple idea meaningful?

There is only one stage, so no carry rippling occurs; delay is a single

t_{c}

and

C_{1}

is the only carry-out — the degenerate case where RCA and a lone Full adder coincide.

Edge case: can signed overflow occur when adding two numbers of opposite sign?

No — adding a positive and a negative number always lands within range, so

C_{n} \oplus C_{n - 1} = 0

there; signed overflow requires two same-sign operands.

Edge case: what is the widest possible carry chain actually exercised when adding

A = 0000

and

B = 0000

with

C_{0} = 0

Zero-length — every stage generates and propagates nothing, so no carry moves; the worst-case

n \cdot t_{c}

is a bound, not what every input pattern triggers.

Connections

Ripple-carry adder — the parent this bank drills.
Full adder · Half adder — the single-bit blocks behind every item.
Two's complement · Overflow detection — the subtraction and overflow traps.
Propagation delay · Carry-lookahead adder — the timing traps and their cure.
Combinational circuits — why "ripple" is delay, not memory.