Half adder and full adder: Worked examples — Hardware deep dive

Before we touch numbers, one reminder of the tools, spelled out so nobody is lost:

Recall the equations we are testing (from the parent), now with $A B$ read as $A \cdot B$ : $Half: S = A \oplus B, C = A \cdot B$ $Full: S = A \oplus B \oplus C_{in}, C_{o u t} = A B + A C_{in} + B C_{in}$

The schematics below show both cells at gate level. Keep them beside you as we work — every example below points back to a specific gate in these pictures, so you can see which wire fired.

The half-adder schematic (above) has exactly two gates: the XOR on top drives the Sum wire, the AND below drives the Carry wire. Examples 2 and 3 are literally "which of these two gates lights up?"

The full-adder schematic (above) is two half adders plus one OR on the carries. In Examples 4 and 5, watch the amber OR output: it fires whenever either half-adder carry ( $C_{1}$ from HA1 or $C_{2}$ from HA2) is 1 — that is the majority rule made physical.

The scenario matrix

Every input situation a single adder cell (or a chain of them) can face falls into one of these classes. Each worked example below is tagged with the cell it covers.

Cell	Case class	What makes it special	Covered by
Z	All inputs zero (degenerate)	Nothing to add — outputs must stay 0	Ex 1
H1	Half adder, exactly one input high	The "carry must NOT fire" case	Ex 2
H2	Both HA inputs high	The classic $1 + 1 = 10$ carry	Ex 3
F1	Full adder, exactly one input high	Only the incoming carry (or one bit) is 1 → $S = 1$ , no carry-out	Ex 6 (col 2)
F-even	Full adder, even count of 1s with a carry	Two 1s → $S = 0$ yet carry-out still fires (majority)	Ex 4
F-max	Full adder, all three high (limit)	Largest single-cell output = $1 1_{2} = 3$	Ex 5
Ripple	Multi-column chain, carry propagates far	$C_{o u t}$ of one feeds $C_{in}$ of next	Ex 6
Overflow	Chain result outgrows its bit-width	The leftmost carry escapes	Ex 7
Word	Real-world word problem	Translate a story into adder cells	Ex 8
Twist	Exam trap / subtraction reuse	Adder doing subtraction via two's complement	Ex 9

Worked examples

Worked example Ex 4 — Cell F-even: even count, yet a carry fires (

$A = 1, B = 0, C_{in} = 1$ ) Now a carry arrives from the previous column. There are two 1s here — an even count — so watch the surprise. In the second schematic, trace $C_{2}$ from HA2 into the amber OR.

Forecast: does $C_{o u t}$ fire even though $A$ and $B$ are never both 1?

$S = 1 \oplus 0 \oplus 1 = 0$ . Why this step? Two of the three inputs are 1 — an even count — so XOR lands back at 0. (Trace it: $1 \oplus 0 = 1$ , then $1 \oplus 1 = 0$ .)
$C_{o u t} = A B + A C_{in} + B C_{in} = (1 \cdot 0) + (1 \cdot 1) + (0 \cdot 1) = 0 + 1 + 0 = 1$ (" $+$ " = OR). Why this step? Majority rules: at least two inputs are 1 (here $A$ and $C_{in}$ ), so the carry fires even though $A \cdot B$ alone did not. In the schematic this is HA2's carry $C_{2} = (A \oplus B) C_{in}$ feeding the OR.

Answer: $(C_{o u t}, S) = (1, 0) = 1 0_{2} = 2$ . Verify: arithmetic column $1 + 0 + 1 = 2 = 1 0_{2}$ . ✓ Key lesson: an even number of 1s gives $S = 0$ , but a carry can still be born from the incoming carry, not just from $A$ and $B$ .

Now we chain cells. The picture below shows three full adders wired in a row — study which wire carries what before the next examples.

Worked example Ex 6 — Cells Ripple + F1:

$A = 01 1_{2} + B = 00 1_{2}$ (three-bit chain) Columns numbered from the right, starting at 0. Initial carry into column 0 is $0$ . Column 2 below is the F1 edge case (exactly one input — the incoming carry — is high). (All " $+$ " inside a column below are arithmetic additions of bit values.)

Forecast: guess the 3-bit result and whether a 4th carry escapes.

Column 0: $A_{0} = 1, B_{0} = 1, C_{in} = 0$ . $S_{0} = 1 \oplus 1 \oplus 0 = 0$ , $C_{o u t} = 1 \cdot 1 = 1$ . Why? Both bits high → carry born, digit 0.
Column 1: $A_{1} = 1, B_{1} = 0, C_{in} = 1$ (the carry from step 1). $S_{1} = 1 \oplus 0 \oplus 1 = 0$ , $C_{o u t} = (1 \cdot 0) + (1 \cdot 1) + (0 \cdot 1) = 1$ . Why? Majority ( $A_{1}$ and incoming carry) fires again — the carry ripples.
Column 2 (Cell F1): $A_{2} = 0, B_{2} = 0, C_{in} = 1$ . $S_{2} = 0 \oplus 0 \oplus 1 = 1$ , $C_{o u t} = 0$ . Why? This is the exactly-one-1 full-adder case: only the incoming carry is high — odd count → $S = 1$ ; no pair of 1s → carry dies here.

Answer: result bits $S_{2} S_{1} S_{0} = 10 0_{2} = 4$ , final carry $0$ . Verify: arithmetic $3 + 1 = 4 = 10 0_{2}$ . ✓ This is exactly a Ripple-carry adder: each $C_{o u t}$ becomes the next $C_{in}$ .

Worked example Ex 7 — Cell Overflow: the carry that escapes (

$A = 11 1_{2} + B = 00 1_{2}$ , 3-bit) What if the answer needs a 4th bit but we only have three columns? (Column " $+$ " = arithmetic.)

Forecast: will the sum fit in 3 bits?

Column 0: bits $1 + 1 + 0$ : $S_{0} = 0$ , carry $= 1$ . Why? $1 \oplus 1 = 0$ ; both high → carry.
Column 1: bits $1 + 0 + 1$ : $S_{1} = 0$ , carry $= 1$ . Why? Even count → $S = 0$ ; majority ( $A_{1}$ , carry-in) → carry.
Column 2: bits $1 + 0 + 1$ : $S_{2} = 0$ , carry $= 1$ . Why? Same as column 1 — carry keeps rippling all the way out.
The escaping carry is the 4th bit: $C_{o u t} = 1$ .

Answer: full result $C_{o u t} S_{2} S_{1} S_{0} = 100 0_{2} = 8$ . If the register is only 3 bits wide, the stored value is $00 0_{2} = 0$ and the final carry is a carry/overflow flag. Verify: arithmetic $7 + 1 = 8 = 100 0_{2}$ . ✓ Lesson: a fixed-width adder can overflow; the leftmost $C_{o u t}$ tells you it happened.

Worked example Ex 8 — Cell Word: a real-world tally

A vending machine counts coins with a 4-bit register. It currently holds $9$ coins ( $100 1_{2}$ ) and $6$ more ( $011 0_{2}$ ) drop in at once. Using full adders per column, what does the register read, and does it overflow 4 bits? (Column " $+$ " = arithmetic.)

Forecast: $9 + 6 = 15$ — will it fit in 4 bits (max $15$ )?

Col 0: bits $1 + 0 + 0$ : $S_{0} = 1$ , carry $0$ . Why? One 1, odd → $S = 1$ ; no pair → no carry.
Col 1: bits $0 + 1 + 0$ : $S_{1} = 1$ , carry $0$ . Why? Same shape as col 0.
Col 2: bits $0 + 1 + 0$ : $S_{2} = 1$ , carry $0$ . Why? Same.
Col 3: bits $1 + 0 + 0$ : $S_{3} = 1$ , carry $0$ . Why? One 1 → $S = 1$ ; no carry escapes.

Answer: register $= S_{3} S_{2} S_{1} S_{0} = 111 1_{2} = 15$ , no overflow. Verify: arithmetic $9 + 6 = 15 = 111 1_{2}$ , and $15 \leq 15$ so it fits exactly at the limit. ✓ One coin more would overflow — the register sits right at its ceiling.

Worked example Ex 9 — Cell Twist: an adder doing

subtraction ( $5 - 3$ in 4-bit two's complement) The exam favourite: the same full-adder chain performs subtraction if we feed it the two's complement of the number being subtracted, with $C_{in} = 1$ at column 0. (Column " $+$ " = arithmetic.)

Forecast: compute $5 - 3$ and predict the final carry (a hint about sign).

Represent operands: $5 = 010 1_{2}$ , $3 = 001 1_{2}$ . Why this step? We add $5$ and $(- 3)$ ; $- 3$ needs a two's-complement form. See Two's complement subtraction.
Form $- 3$ : invert $0011 \to 1100$ , then add 1 $\to 110 1_{2}$ . Why? Two's complement of $x$ is (flip all bits) $+ 1$ ; that value acts like $- 3$ in modular addition.
Add with $C_{in} = 1$ already folded in (the $+ 1$ above did it). Add $0101 + 1101$ column by column:
- Col 0: bits $1 + 1 + 0$ : $S_{0} = 0$ , carry $1$ .
- Col 1: bits $0 + 0 + 1$ : $S_{1} = 1$ , carry $0$ .
- Col 2: bits $1 + 1 + 0$ : $S_{2} = 0$ , carry $1$ .
- Col 3: bits $0 + 1 + 1$ : $S_{3} = 0$ , carry $1$ (escapes). Why each? Ordinary full-adder rules; nothing new — that's the whole point.
Discard the escaping 4th carry. Why? In two's-complement subtraction the final carry-out is expected and simply dropped; a carry-out of 1 here signals the result is non-negative.

Answer: result bits $S_{3} S_{2} S_{1} S_{0} = 001 0_{2} = 2$ . Verify: arithmetic $5 - 3 = 2 = 001 0_{2}$ . ✓ The adder never changed — only what we fed it did. This is why one circuit family serves both $+$ and $-$ .

Recall Rebuild the matrix (say the "why" out loud each time)

Cover the answers and re-derive $(C_{o u t}, S)$ for: all-zeros, one-high, both-high, all-three-high. Then chain $011 + 001$ . All-zeros — why? ::: Count of 1s is 0 (even) so XOR gives $S = 0$ ; no AND-product fires so $C = 0$ . Answer $(0, 0) = 0$ . Both-high half adder — why? ::: Equal bits don't differ so XOR gives $S = 0$ ; both high so AND fires $C = 1$ . Answer $(1, 0) = 2$ . Full adder with even count (two 1s) — why? ::: Two is even so XOR gives $S = 0$ ; but two 1s meet the majority so $C_{o u t} = 1$ . Answer $(1, 0) = 2$ . All-three-high full adder — why? ::: Three is odd so XOR gives $S = 1$ ; at least two 1s so majority gives $C_{o u t} = 1$ . Answer $(1, 1) = 3$ . $01 1_{2} + 00 1_{2}$ — why? ::: Carry born in col 0, ripples through col 1 (majority), dies in col 2 (only one 1). Answer $10 0_{2} = 4$ . $5 - 3$ via two's complement — why? ::: Add $5$ to two's complement of $3$ ; ordinary adder rules; drop the escaping carry (result non-negative). Answer $001 0_{2} = 2$ .

Connections

Half adder and full adder — the parent equations these examples test
Ripple-carry adder — the chaining used in Ex 6–8
Carry-lookahead adder — how to avoid the slow ripple of Ex 7
Two's complement subtraction — the subtraction trick of Ex 9
XOR gate, AND gate, OR gate — the gates behind Sum and Carry
Truth tables and minterms — the derivation style
Combinational circuits — the parent family

Worked examples — Half adder and full adder

The scenario matrix

Worked examples

Connections

Concept Map