Half adder and full adder: Question bank — Hardware deep dive

Picture the gates before you trap them

Before any true/false line, anchor the three gate behaviours in one picture. Each column below the gate name shows the output for the four input pairs — look at the single cell where they disagree: that lone difference is the entire half adder.

The half adder as a circuit

The half adder is just those two panels wired in parallel from the same two inputs. Trace the two wires in the figure: $A$ and $B$ fan out, one copy goes into an XOR (giving $S$ ), the other into an AND (giving $C$ ).

The full adder in one truth-table picture

All eight input combinations at once — this single visual anchors both explanations used throughout the trap questions. The orange bars mark rows where the count of 1s is odd (those give $S = 1$ , the parity story); the blue shading marks rows where at least two inputs are 1 (those give $C_{o u t} = 1$ , the majority story).

Why the two carry formulas are the same circuit

The trap line " $C_{o u t} = A B + (A \oplus B) C_{in}$ vs $A B + A C_{in} + B C_{in}$ are different" is false — here is the collapse, step by step, so you never take it on faith.

The bar chart below verifies the collapse by brute force: for all eight inputs the two formulas produce identical heights (both light up on exactly the four majority rows).

The full adder built from two half adders

The trap questions about $C_{1}$ , $C_{2}$ and the final OR all refer to this signal flow. Follow the arrows: HA1 takes $A, B$ ; its Sum $S_{1} = A \oplus B$ travels into HA2 together with $C_{in}$ ; HA2's Sum is the final $S$ . The two half-adder carries $C_{1}$ and $C_{2}$ meet at an OR gate to make $C_{o u t}$ .

True or false — justify

The half adder's Sum output equals the OR of its inputs.

False — Sum is XOR. OR gives 1 for the pair

(1, 1)

, but adding the two 1s should make Sum

= 0

with a carry; XOR correctly outputs 0 when the bits are equal.

A half adder can add two bits that already came with a carry from the previous column.

False — that is exactly what "half" denies: it has no

C_{in}

input, so it only ever sees two bits and is incomplete for chaining.

A full adder always produces a 2-bit result

(C_{o u t}, S)

no matter which inputs you feed it.

True — three input bits sum to at most the value

3 = 1 1_{2}

, which always fits in exactly two output bits.

The full adder Sum

S = A \oplus B \oplus C_{in}

is 1 whenever a majority of the inputs are 1.

False — Sum tracks parity (odd count of 1s), not majority. For

A = B = 1, C_{in} = 0

the majority is 1 but Sum

= 0

Swapping the roles of

A

and

C_{in}

in a full adder changes its outputs.

False — all three inputs enter symmetrically (

S

is parity,

C_{o u t}

is majority), so any permutation of

A, B, C_{in}

gives identical outputs.

C_{o u t} = A B + (A \oplus B) C_{in}

and

C_{o u t} = A B + A C_{in} + B C_{in}

describe different circuits.

False — they are algebraically equal (see the collapse and bar chart above); the second is the plain majority form, the first is the form that falls out when you build the full adder from two half adders.

A full adder made from two half adders needs an OR gate that the direct majority-form circuit does not obviously show.

True — the two internal half-adder carries

C_{1}

and

C_{2}

can never both be 1, so their combination is an OR:

C_{o u t} = C_{1} + C_{2}

Spot the error

"Half-adder carry is

C = A + B

because addition is like OR."

Error: OR fires for

(0, 1)

and

(1, 0)

, but adding those gives no carry. Carry must be AND (

A \cdot B

), true only when both bits are 1.

"Full-adder Sum is

A + B + C_{in}

since 'sum' means add."

Error: here

+

is Boolean OR, not arithmetic addition. Sum is parity, so

S = A \oplus B \oplus C_{in}

"For the majority carry I can write

C_{o u t} = A B \cdot B C_{in} \cdot A C_{in}

Error: majority means "at least one pair is both-1", which is an OR of the pair-products:

A B + B C_{in} + A C_{in}

, not their AND.

"When I build a full adder from two half adders, the second half adder should add

A

and

C_{in}

Error: the second half adder adds the first half adder's Sum

S_{1} = A \oplus B

with

C_{in}

, not the raw

A

"A ripple-carry adder wires each stage's

C_{o u t}

back into the same stage's

C_{in}

Error: a stage's

C_{o u t}

feeds the next stage's

C_{in}

; feeding it back into itself would be a loop, not a ripple chain.

"Because

C_{o u t}

can equal 1, one full adder alone can output the value 4."

Error: a single cell outputs at most the value

3

;

(C_{o u t}, S)

is only two bits. The value 4 needs the carry to ripple into a second stage.

Why questions

Why does any binary adder cell need two outputs rather than one?

Because adding two 1s gives the value

2 = 1 0_{2}

, a two-bit answer, so one column must produce both a current bit (Sum) and a spill into the next column (Carry).

Why is Sum an XOR and not something else?

XOR outputs 1 exactly when the count of 1-inputs is odd; the low bit of any sum equals the parity of its addends, which is precisely what XOR encodes.

Why is the full-adder carry called the "majority function"?

C_{o u t} = 1

exactly when two or three of the inputs are 1 — the value held by the majority of the three inputs.

Why can we reuse two half adders to make a full adder instead of designing new logic?

Adding three bits factors into "add two, then add the third to that partial sum", and each of those two-bit additions is exactly a half adder.

Why do the two internal half-adder carries

C_{1}

and

C_{2}

never both equal 1 at the same time?

C_{1} = A B

needs

A = B = 1

, but then

S_{1} = A \oplus B = 0

, so

C_{2} = S_{1} \cdot C_{in} = 0

. They are mutually exclusive, which is why an OR safely combines them into

C_{o u t}

Why does XOR give the correct Sum for three inputs when we only defined it for two?

XOR is associative —

(A \oplus B) \oplus C_{in}

equals

A \oplus (B \oplus C_{in})

because both just answer "is the total count of 1s odd?", a fact independent of grouping — so we can chain the two-input gate and it flips output once per 1-input, landing on 1 for an odd total.

Why is a full adder the right building block for two's-complement subtraction?

Subtraction becomes "add the two's complement", so the same full-adder chain does subtraction by feeding a complemented operand plus a starting

C_{in} = 1

Edge cases

What are

S

and

C

of a half adder when

A = 0, B = 0

Both 0 — the degenerate case: nothing to add, nothing to carry, so the outputs are the neutral

(0, 0)

Full adder with all inputs 0 — what is

(C_{o u t}, S)

(0, 0)

: zero 1-inputs means even parity (Sum 0) and no majority of 1s (Carry 0).

Full adder with exactly two inputs 1 (e.g.

A = B = 1, C_{in} = 0

) — what is

(C_{o u t}, S)

(1, 0)

: two 1s is a majority so

C_{o u t} = 1

, but an even count means parity 0 so

S = 0

— the classic case where Sum and Carry disagree.

Full adder with all inputs 1 — why is Sum 1 rather than 0?

Three 1s is an odd count, so parity is 1;

S = 1

while

C_{o u t} = 1

too, giving

1 1_{2} = 3

If exactly one of the three full-adder inputs is 1, what happens to

C_{o u t}

C_{o u t} = 0

— a single 1 is never a majority of three, so no carry spills out regardless of which input it is.

In a ripple-carry adder, what is the

C_{in}

of the very first (least-significant) stage?

0 for ordinary addition — there is no earlier column to carry from, so the chain starts clean.

Is there any input to a single full adder that makes

C_{o u t} = 1

while

S = 1

Yes, only when all three inputs are 1: majority gives

C_{o u t} = 1

and odd parity gives

S = 1

, i.e.

3 = 1 1_{2}

If you accidentally tie a full adder's

C_{in}

permanently to 1, what does it compute?

The value

A + B + 1

in ordinary arithmetic — it always adds an extra 1, which is exactly the trick used to start a subtractor chain, but wrong for plain addition.

Connections

Half adder and full adder — the parent note these traps drill
XOR gate, AND gate, OR gate — the gate meanings every answer relies on
Truth tables and minterms — how each equation was derived
Ripple-carry adder and Carry-lookahead adder — where chaining edge cases matter
Two's complement subtraction — reusing the adder for subtraction
Combinational circuits — the parent family